
Interrupt and Exception Handling
MOTOROLA
MC68322 USER’S MANUAL
5-5
ENBx—External Interrupt Enable
External interrupts are enabled when set and disabled when cleared. This bit affects the
interrupt to the core, but not the interrupt event in the STSx or REQx fields.
STSx—External Interrupt Status
This bit reflects the status of the corresponding IRQ signal after it is synchronized with CLK1.
REQx—External Interrupt Request
This bit is set when an external interrupt event occurs. To remove the interrupt, the core
should write a 1 to the REQx bit. If this bit and the ENBx bit are set, an interrupt is posted.
Interrupt Level Register
This field is used to set the interrupt level. A level 7 is the highest priority and level 1 is the
lowest priority. Level 0 indicates that the interrupt is disabled.
MODEx—External Interrupt Mode
This field controls the external interrupt polarity and whether it is level sensitive or edge
sensitive. Table 5-2 lists the MODEx field encodings.
SENx—External Interrupt (Software Enable)
This bit is only used when the external interrupt is level sensitive. SENx is only set by the
software and only cleared by the hardware. It allows the software to control a level-sensitive
interrupt without using the ENBx bit. The software cannot clear SENx, but it is set by the
software and cleared by the hardware when a level-sensitive interrupt is received. This bit
is also forced clear if the MODEx field is set for edge-sensitive interrupts (10
2 or 112). When
an external interrupt occurs, REQx is set and SENx is automatically cleared.
Because a level-sensitive interrupt may not change, caution must be taken so that the core
is not constantly interrupted. It is recommended that an external interrupt be disabled before
the SENx field in the external interrupt register is initialized by the software.
Table 5-2. External Interrupt Polarity
ENCODING
DESCRIPTION
00
Active Low Level
01
Active High Level
10
Falling Edge Transition
11
Rising Edge Transition
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