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| 型號(hào)： | MC68322FT16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.667 MHz, RISC PROCESSOR, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 241/283頁(yè) |
| 文件大?。?/td> | 1602K |
| 代理商： | MC68322FT16 |
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MOTOROLA
MC68322 USER’S MANUAL
5-1
SECTION 5
INTERRUPT AND EXCEPTION HANDLING
The MC68322 supports two types of interrupts—internal and external. These interrupts are
posted to the EC000 core through an internal interrupt controller, which uses an exception
processing routine to handle the interrupt. The core’s internal status register contains a 3-bit
interrupt priority mask that ranges from level 0 to 7 (level 7 being the highest) mask level.
Interrupts are inhibited for all priority levels less than or equal to the current mask level.
Priority level 7 is a special case. Level 7 interrupts cannot be inhibited by the interrupt priority
mask, thus providing a nonmaskable interrupt capability. Level 7 interrupts can be
generated in two ways. First, an interrupt is generated each time the interrupt event level
changes from a level below level 7. Second, a level 7 interrupt occurs if the interrupt request
level is a 7 and the core priority mask is dropped from level 7 to a lower level by the
execution of an instruction.
5.1 INTERNAL INTERRUPTS
The MC68322 modules function simultaneously and independently of the core. At the
completion of a module’s operation, the module is capable of posting an internal interrupt to
the core through an internal interrupt controller. For example, the printer video controller
(PVC) could post a page-end interrupt to signal the core that it has finished rendering a
page. The controller ranks the interrupt based on a module’s programmed interrupt priority
level and then posts the interrupt event to the core. This type of internal interrupt event is
called a hardware interrupt because it is initiated by one of the MC68322 modules.
The MC68322 supports another type of interrupt event called a software interrupt. This type
of interrupt is initiated by the software by programming some internal registers on the
MC68322. Once the software has initiated such an event, the interrupt will be posted to the
core in exactly the same way as a hardware interrupt event. The advantage that these
MC68322 hardware interrupts provide over the typical 68000 Family software exceptions is
that these software interrupts can be set at a lower priority level than the current interrupt
event and thus be delayed until the core runs at a lower priority level. This causes the
software interrupt to be serviced sometime between the current interrupt and the next
noninterrupt operation. See Section 5.4.2.3 Instruction Traps for more information.
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