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參數(shù)資料
| 型號： | MC72000 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Integrated Bluetooth Radio |
| 中文描述： | 集成藍牙無線 |
| 文件頁數(shù)： | 111/156頁 |
| 文件大小： | 1782K |
| 代理商： | MC72000 |
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MOTOROLA
MC72000
Advance Information Data Sheet
Go to: www.freescale.com
111
7.4.6.1.2
Network Mode
Network mode is used for creating a time division multiplexed (TDM) network, such as a TDM CODEC
network or a network of DSPs. This mode only operates with continuous clock mode. A frame sync occurs
at the beginning of each frame. In this mode, the frame is divided into more than one time slot. During each
time slot, one data word can be transferred. Each time slot is then assigned to an appropriate CODEC or
DSP on the network. The DSP can be a master device that controls its own private network, or a slave device
that is connected to an existing TDM network and occupies a few time slots.
The frame sync signal indicates the beginning of a new data frame. Each data frame is divided into time
slots and transmission and/or reception of one data word can occur in each time slot (rather than in just the
frame sync time slot as in normal mode). The frame rate dividers, controlled by the DC[4:0] bits, select two
to thirty-two time slots per frame. The length of the frame is determined by the following factors:
The period of the serial bit clock (PSR, PM[7:0] bits for internal clock, or the frequency of the
external clock on the STCK and/or SRCK pins).
The number of bits per sample (WL[1:0] bits).
The number of time slots per frame (DC[4:0] bits).
In network mode, data can be transmitted in any time slot. The distinction of the network mode is that each
time slot is identified with respect to the frame sync (data word time). This time slot identification allows
the option of transmitting data during the time slot by writing to the STX register or ignoring the time slot
by writing to STSR. The receiver is treated in the same manner, except that data is always being shifted into
the RXSR and transferred to the SRX register. The core reads the SRX register and either uses it or discards
it.
Figure 74 and Figure 75 show sample timing of network mode transfers. The figures show receive and
transmit frames of 5 time-slots for each. The numbered circles and arrows in the figure identify discussion
notes which are contained in Table 56 and Table 57.
7
At the end of the transmit word, the STXD pin
continues to drive
In the general case where STCK is driven
externally, the transmitter does not know when
the normal end of the list bit time is.
Transmit status flag update
8
TDE bit is set
The TFE bit is set if the level of data in
the TXFIFO falls below the watermark
level
Transmit interrupt occurs when TFE set
9
If the TIE bit is set, enabling transmit interrupts,
then:
(Other options for processing the data is either
polling or DMA transfers.)
Repeat at step 1 on the next frame sync
2
Transmit interrupt
occurs when TDE set
1.See the description of the ROE bit in Section 7.4.5.2.8, “SSI Control/Status Register (SCSR),” for a description of
what happens when the ROE bit is set.
2.The frame sync must not occur earlier than what is configured in the SRXCR as documented in Section 7.4.5.2.7,
“SSI Transmit and Receive Control Registers (STXCR, SRXCR).”
Table 55. Gated Clock Operations (Continued)
Step
FIFOs Disabled
(See Figure 73)
FIFOs Enabled
(No Figure Available
F
Freescale Semiconductor, Inc.
For More Information On This Product,
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