參數(shù)資料
型號(hào)： MC72000
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍(lán)牙無線
文件頁數(shù)： 84/156頁
文件大?。?/td> 1782K
代理商： MC72000
84
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
Figure 51. STX Register Diagram
7.4.5.2.2
SSI Transmit FIFO Register (TXFIFO)
The TXFIFO is a 7 x 16 bit register used to buffer samples written to the transmit data register (STX). It is
written by the contents of STX whenever the transmit FIFO feature is enabled. When enabled, the transmit
shift register (TXSR) receives its values from this FIFO register. If the transmit FIFO feature is not enabled,
this register is bypassed and the contents of STX are transferred into the TXSR.
When the transmit interrupt enable (TIE) bit in the SCR2 and transmit data register empty (TDE) bit in the
SCSR are set, the transmit interrupt is asserted whenever STX is empty and the data level in the SSI transmit
FIFO falls below the selected threshold.
When both TXFIFO and STX are full, any further write will overwrite the contents of TXFIFO and STX.
NOTE:
Enable SSI before writing to TXFIFO and STX.
7.4.5.2.3
SSI Transmit Shift Register (TXSR)
TXSR is a 16-bit shift register that contains the data being transmitted. When a continuous clock is used,
data is shifted out to the serial transmit data (STXD) pin by the selected (internal/external) bit clock when
the associated (internal/external) frame sync is asserted. When a gated clock is used, data is shifted out to
the STXD pin by the selected (internal/external) gated clock. The word length control bits (WL[1:0]) in the
SSI transmit control register (STXCR) determine the number of bits to be shifted out of the TXSR before it
is considered empty and can be written to again. See Section 7.4.5.2.7, “SSI Transmit and Receive Control
Registers (STXCR, SRXCR),” for more information. This word length can be 8, 10, 12, or 16 bits. The data
to be transmitted occupies the most significant portion of the shift register. The unused portion of the
register is ignored. Data is always shifted out of this register with the most significant bit (MSB) first when
the SHFD bit of the SCR2 is cleared. If this bit is set, the least significant bit (LSB) is shifted out first.
See Figure 52 and Figure 53 for more information.
Base + 0x00
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
DATA[15:0]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
F
For More Information On This Product,
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