參數資料
型號： MC72000
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍牙無線
文件頁數： 118/156頁
文件大?。?/td> 1782K
代理商： MC72000
118
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
Figure 78. Network Mode Receive Timing with Mask Register
Table 59. Notes for Receive Timing with Mask Register in Figure 78
Note
Source
Signal
Destination
Signal
Description
6
Example of a 5 time-slot frame, receiving data from time-slots 0 and 2. Note that
the receive hardware will only obtain data on the SRXD pin when the RSMn bit is
set to 1.
Example with bit-length frame sync and standard timing (RFSI=0, RFSL=1,
REFS=0). Frame timing begins with the rising edge of SRFS.
Data on the SRXD pin is sampled on the falling edge of SRCK and shifted into
the RXSR register.
At the word clock, the data in the RXSR register is transferred to the SRX
register, for enabled time-slots.
This flag is set for each word clock (time-slot) where the RSMn bit is set, to
indicate that data is available to be processed. The software must keep track of
the time-slots as they occur so it knows which data it is processing.
If the receive interrupts are enabled (RIE=1), an interrupt will be generated when
this status flag is set. The software reads the SRX register to clear the interrupt
(see Section 7.4.9.2, “Description of Interrupt Operation,” for a complete
description of interrupt processing).
7
SRFS
8
SRXD
RXSR
register
9
RXSR
register
SRX register
10
RDR status
flag and
receive
interrupt
TS 0
TS 1
TS 2
TS 3
TS 4
TS 0
RSM[0]
RSM[1]
RSM[2]
RSM[3]
RSM[4]
RSM[0]
0
1
2
3
4
0
time-slot
Continuous SRCK
internal word clock
SRFS
RSMn bits usage
RTSCNT field of SFSR register
SRXD
RXSR register
SRX register
RDR status bit/interrupt
Valid
Indefinite transition depends on SW interrupt processing
Invalid
6
7
8
9
10
F
For More Information On This Product,
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