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參數(shù)資料
| 型號(hào)： | MC72000 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Integrated Bluetooth Radio |
| 中文描述： | 集成藍(lán)牙無(wú)線 |
| 文件頁(yè)數(shù)： | 76/156頁(yè) |
| 文件大?。?/td> | 1782K |
| 代理商： | MC72000 |
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76
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receive FIFO full bit, RF, becomes set. Software clears the RF
bit by reading the RX data register.
7.3.8.4 Slave Mode Operation
The CSPI operates in slave mode when the MODE bit is clear. In slave mode, the SPI_CK pin is the input
for the serial clock from the ARM7. Before a data transmission occurs, the SS_B pin of the slave CSPI must
be at logic zero. SS_B must remain low until the transmission is complete.
If the CSPI is configured as slave, the user can set the CSPI control register to match the external CSPI
master’s setting for PHA and POL. SS_B becomes an input signal and is used for capturing data in the
internal receive shift register and for loading data to the internal transmit data shift register. This also
increments the TXFIFO and RXFIFO.
In a slave CSPI module, data enters the shift register under the control of the serial clock from the master
CSPI module. After a word enters the shift register of a slave CSPI, it transfers to the receive FIFO data
register, and the receive FIFO count is incremented. To prevent an overflow condition, slave software then
must read the receive data FIFO register before another full word enters the shift register.
The maximum frequency of the SPI_CK for a CSPI configured as a slave must be less than one-fourth the
bus clock speed. The frequency of the SPI_CK for a CSPI configured as a slave does not have to correspond
to any CSPI baud rate. The baud rate only controls the speed of the SPI_CK generated by a CSPI configured
as a master. Therefore, the frequency of the SPI_CK for a CSPI configured as a slave can be any frequency
less than one-fourth the bus speed.
When the master CSPI starts a transmission, the data in the slave shift register begins shifting out on the
MISO pin. The slave can load its shift register with a new word for the next transmission by writing to its
transmit data FIFO register. The slave must write to its transmit data FIFO register at least eight bus cycles
before the master ends the last word transmission. Otherwise, the word already in the slave shift register
shifts out on the MISO pin.
7.3.9 Timing Diagrams
Figure 44. Master CSPI Timing Using DATAREADY_B Edge Trigger
SS_B
DATAREADY_B
SPI_CK, MOSI, MOSI
t1
t2
t3
t4
t5
F
For More Information On This Product,
n
.
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| MC7220C-100M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-20C 20 CORE 100M |
| MC7220C-25M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-20C 20CORE 25M 制造商:pro-power 功能描述:CABLE, DEF 7-2-20C, 20CORE, 25M |
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| MC7225C-25M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-25C 25CORE 25M 制造商:pro-power 功能描述:MULTICORE, 25, 7/0.2MM, 25M, BLACK 制造商:pro-power 功能描述:CABLE, DEF 7-2-25C, 25CORE, 25M 制造商:PRIVATE LABEL 功能描述:CABLE, DEF 7-2-25C, 25CORE, 25M, Reel Length (Imperial):82ft, Reel Length (Metri |
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