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MC72000 Advance Information Data Sheet
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MOTOROLA
Package Pinout
Not all power supply pins including ground pins are described in the following pin description list as all of
these pins share the same name within the three power groups. Refer to Section 10, “Applications
Information,” for details on how to isolate and identify the correct configuration for the power supply pins.
Table 15. Pin Descriptions
RF Signals
DCLF1
Data Clock Loop Filter charge pump output for external loop filter.
MNLF
Main Frac-N Loop Filter (Charge Pump). The external loop filter is referenced to VCC_RF in order
to minimize transmit phase noise.
XEMIT
Reference oscillator emitter. A bias current of 50
μ
A is supplied internally to the emitter. This pin
must be left open if external (not crystal) reference frequency is used.
XBASE
Reference oscillator base. The base is the reference oscillator input. An on-chip capacitor trim
network is also included to allow the user to use relatively inexpensive crystals. This pin is also the
feed-point in case of using external (not crystal) reference frequency.
RFTEST+
This pin is for factory use only. It must be left open.
RFTEST-
This pin is for factory use only. It must be left open.
RFIN
RFIN is the RF input to the LNA. The LNA is a bipolar cascode design. The input is the base of the
common emitter transistor. Minimum external matching is required to optimize the input return loss
and gain. The cascode output drives the primary of an on-chip balun single-ended.
PAOUT+
Positive differential PA output. An external differential-to-single-ended matching network is desired.
PAOUT-
Negative differential PA output. An external differential-to-single-ended matching network is
desired.
EPAEN
External PA enable is a digital output which can be used to enable an external PA. It is normally
placed under sequence manager control. This output can also be used to control an external Rx/Tx
switch requiring complementary drive.
EPADRV
External PA driver DAC output. Analog output ranges from 0.02 to VCC_RF - 0.02. The EPADRV is
linearly scaled to a maximum VCC_RF
of 3.1 V.
GPO
The General Purpose Output is a digital output. GPO is normally controlled by the internal
sequence manager but may also be programmable. This signal is typically used to control an
external Rx/Tx switch.
Baseband Clock, Reset, and JTAG Signals
EXTAL_BB
32.768 kHz baseband external crystal clock input. In case of using external clock, the signal must
be fed to this pin, while leaving XTAL pin open.
XTAL_BB
32.768 kHz baseband crystal clock output. This pin must be left open in case of using external
clock.
TDI
The test data input pin provides a serial input data stream to all TAP controllers. TDI is sampled on
the rising edge of TCK. Leave open if JTAG is unused.
TDO
The test data output pin is tri-statable, providing serial output data from the Master TAP or ARM
Core TAP controller. It is actively driven in the shift-IR and shift-DR controller states of the TAP
controller state machine. TDO changes on the falling edge of TCK.
F
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