參數(shù)資料
型號: MC72000
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Integrated Bluetooth Radio
中文描述: 集成藍牙無線
文件頁數(shù): 68/156頁
文件大小: 1782K
代理商: MC72000
68
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
7.3.7.3 Control Register (CONTROLREG)
Figure 38. Control Register (CONTROLREG)
CONTROLREG is a 32-bit register. The high 16 bits are reserved bits and are always read as 0. The control
registers, DRCTL, SPIRDY, MODE, SSPOL, SSCTL, PHA, POL, and BITCOUNT should not be changed
when SPIEN = 1 to ensure that the internal counters and control logic are properly reset.
DRCTL[2:0]—Data Rate Control
This bit field selects the bit rate of the SCLK based on the division of the CPU clock.Table 30 shows
the DRCTL[2:0] bit rate encoding.
Table 30. DRCTL[2:0] Bit Rate Encoding
SPIRDY[1:0]—DATAREADY_B Control
In master mode, these two bits select the wave form of the DATAREADY_B input signal. In slave mode
they are don’t care. Table 31 shows the SPIRDY[1:0] encoding.
Table 31. SPIRDY Control Encoding
MODE—CSPI Mode Select
This bit selects the CSPI mode.
1 = CSPI is master mode
0 = CSPI is slave mode
Register address: Base + 0x08
31
30
29
28
27
26
25
24
Reserved
0
23
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
7
6
5
4
3
2
1
0
R
W
DRCTL[2:0]
SPIRDY[1:0]
MOD
E
0
SPIEN
SSPOL SSCTL
PHA
POL
BITCOUNT[3:0]
XCH
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRCTL[2:0]
Function
000
001
010
011
100
101
110
111
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 128
Divide by 256
Divide by 512
SPIRDY[1:0]
Function
00
01
10
11
Don’t care DATAREADY_B
Falling edge trigger input
Active low level trigger input
Reserved
F
For More Information On This Product,
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