參數(shù)資料
型號： MC72000
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍牙無線
文件頁數(shù)： 70/156頁
文件大?。?/td> 1782K
代理商： MC72000
70
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
7.3.7.4 Interrupt Control/Status Register (INTREG)
Figure 39. Interrupt Control/Status Register (INTREG)
INTREG is a 32-bit register. The high 16 bits are reserved bits and are always read as 0.
TE—TXFIFO Empty Status
The TE bit is forced to 0 when the SPIEN is zero and will change to 1 after SPIEN is set.
1 = The TXFIFO is empty but data shifting may still be on-going
To make sure no data transaction is on-going, read the XCH bit in the CONTROLREG.
0 = At least one data word is in the TXFIFO
TH—TXFIFO Half Status
The TH bit is forced to 0 when the SPIEN is zero and will change to 1 after SPIEN is set.
1 = More than or equal to 4 empty slots in the TXFIFO
0 = Less than 4 empty slots in the TXFIFO
TF—TXFIFO Full Status
1 = 8 data words in the TXFIFO
0 = Less than 8 data words in the TXFIFO
RR—RXFIFO Data Ready Status.
1 = At least one data word is ready in the RXFIFO
0 = The RXFIFO is empty
RH—RXFIFO Half Status
1 = More than or equal to 4 data words in the RXFIFO
0 = Less than 4 data words in the RXFIFO
RF—RXFIFO Full Status
1 = 8 data words in the RXFIFO
0 = Less than 8 data words in the RXFIFO
0001
.
.
.
1110
1111
2-bit transfer
.
.
.
15-bit transfer
16-bit transfer
Register address: Base + 0x0C
31
30
29
28
27
26
25
24
Reserved
0
23
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
TF
1
TH
0
TE
R
W
BOEN
ROEN
RFEN
RHEN
RREN
TFEN
THEN
TEEN
BO
RO
RF
RH
RR
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Table 32. BITCOUNT[3:0] Encoding (Continued)
BITCOUNT[3:0]
Function
F
For More Information On This Product,
n
.
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