參數(shù)資料
型號： MC72000
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍牙無線
文件頁數(shù)： 97/156頁
文件大?。?/td> 1782K
代理商： MC72000
MOTOROLA
MC72000
Advance Information Data Sheet
Go to: www.freescale.com
97
Table 44 shows the clock configuration options.
TSHFD—Transmit Shift Direction
This bit controls whether the MSB or LSB is transmitted first for the transmit section.
1 = LSB is transmitted first.
0 = Data is transmitted MSB first.
NOTE:
The CODEC device labels the MSB as bit 0, whereas the SSI labels the
LSB as bit 0. Therefore, when using a standard CODEC, the SSI MSB (or
CODEC bit 0) is shifted out first, and the TSHFD bit should be cleared.
TSCKP—Transmit Clock Polarity
This control bit determines which bit clock edge is used to clock out data in the transmit section.
1 = Falling edge of the bit clock is used to clock the data out.
0 = Data is clocked out on the rising edge of the bit clock.
SSIEN—SSI Enable
This control bit enables and disables the SSI.
1 = SSI is enabled.
When enabled, causes an output frame sync to be generated when set up for internal frame sync
or causes the SSI to wait for the input frame sync when set up for external frame sync.
0 = SSI is disabled and held in a reset condition.
When disabled, all output pins are tri-stated, the status register bits are preset to the same state
produced by the power-on reset, and the control register bits are unaffected. The contents of the
STX, TXFIFO, and RXFIFO are cleared when this bit is reset. When SSI is disabled, all internal
clocks are disabled except clocks required for register access. When clearing SSIEN, it is
recommended to also clear RE and TE.
NET—Network Mode
This control bit selects the operational mode of the SSI.
1 = Network mode is selected.
0 = Normal mode is selected.
TFSI—Transmit Frame Sync Invert
This control bit selects the logic of frame sync I/O.
1 = Frame sync is active low.
0 = Frame sync is active high.
TFSL—Transmit Frame Sync Length
This control bit selects the length of the frame sync signal to be generated or recognized. See Figure 60
for an example timing diagram of the FS options.
1 = A one-clock-bit-long frame sync is selected.
0 = A one-word-long frame sync is selected.
The length of this word-long frame sync is the same as the length of the data word selected by
WL[1:0].
The frame sync is deasserted after one bit for bit length frame sync and after one word for word length
frame sync.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
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