參數(shù)資料
型號: MC72000
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Integrated Bluetooth Radio
中文描述: 集成藍(lán)牙無線
文件頁數(shù): 51/156頁
文件大小: 1782K
代理商: MC72000
MOTOROLA
MC72000
Advance Information Data Sheet
Go to: www.freescale.com
51
7.2 Universal Asynchronous Receiver/Transmitter (UART)
7.2.1 Overview
Th UART transmits and receives a character length of eight bits. For transmission, data is passed to a
transmitter FIFO (first in, first out), of 32 bytes/characters in depth, from the peripheral data bus. This data
is passed to the shift register and shifted serially out on the TXD pin. For reception, data is received serially
from the RXD pin and stored in a receiver FIFO of 32 bytes/characters in depth. The received data is
retrieved from the receiver FIFO on the peripheral data bus. The receiver and transmitter FIFOs contain a
maskable interrupt that can be configured to interrupt when it reaches a certain level.
The UART-generated baud rate is based upon a configurable divisor and the input clock. It can be
configured to send one or two stop bits as well as odd, even, or no parity. The receiver detects framing errors,
start bit errors, breaks, parity errors, and overrun errors.
The fractional divider is set up by writing an INCrement and MODulo value to registers. It is important that
the UART is disabled (RXE and TXE equal 0) before writing new values to the INC/MOD registers. After
writing to the registers, the receiver and/or transmitter can be enabled (RXE and TXE equal 1).
NOTE:
When the UART is disabled (RXE and TXE equal 0), both the RX and the
TX buffers are flushed, and the status register is updated.
For test purposes, the RXD and TXD pins can be connected internally to each other for loop-back test.
7.2.2 Features
The UART provides the following features:
8 data bits
1 or 2 stop bits
Programmable parity (even, odd, and none)
Four-wire serial interface (RXD, TXD, RTS, and CTS)
Hardware flow control support for RTS and CTS signals
Sense programmable RTS/CTS pins (high true/low true)
Status flags for various flow control and FIFO states
Voting logic for improved noise immunity (16X/8X oversampling)
Two maskable interrupts (IPI_RXRDY, IPI_TXRDY)
Time-out interrupt timer, which times out after eight non-present characters (interrupt on RXRDY)
32-byte receive FIFO and 32-byte transmit FIFO
Receiver and transmitter enable/disable
Low-power modes
Fractional divider to generate any baud rate between 1,200 baud and 1,843.2 kbaud
Software reset
F
Freescale Semiconductor, Inc.
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