- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄359147 > MC72000 (飛思卡爾半導(dǎo)體(中國(guó))有限公司) Integrated Bluetooth Radio PDF資料下載
參數(shù)資料
| 型號(hào)： | MC72000 |
| 廠(chǎng)商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Integrated Bluetooth Radio |
| 中文描述： | 集成藍(lán)牙無(wú)線(xiàn) |
| 文件頁(yè)數(shù)： | 65/156頁(yè) |
| 文件大?。?/td> | 1782K |
| 代理商： | MC72000 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)當(dāng)前第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)
MOTOROLA
MC72000
Advance Information Data Sheet
Go to: www.freescale.com
65
7.3.4 Signal Description
Table 28 shows the signals used to control the serial peripheral interface master.
7.3.5 Detailed Signal Descriptions
The following section provides detailed signal descriptions.
7.3.5.1 SPI_CK — SPI CLOCK
The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the
SPI_CK pin is the clock output. In a slave MCU, the SPI_CK pin is the clock input. In full duplex operation,
the master and slave CSPIs exchange data in BITCOUNT serial clock cycles.
When enabled in the GPIO function select register, the CSPI controls data direction of the SPI_CK pin
regardless of the state of the GPIO data direction register of the shared I/O port.
7.3.5.2 MISO — SPI Master In/Slave Out
MISO is one of the two CSPI module pins that transmits serial data. In full duplex operation, the MISO pin
of the master CSPI module is connected to the MISO pin of the slave SPI module. The master CSPI
simultaneously receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The CSPI is
configured as a slave when its MODE bit is logic zero and its SS_B pin is at logic zero. To support a
multiple-slave system, a logic one on the SS_B pin puts the MISO pin in a high-impedance state.
When enabled in the GPIO function select register the CSPI controls data direction of the MISO pin
regardless of the state of the GPIO data direction register of the shared I/O port.
7.3.5.3 MOSI — SPI Master Out/Slave In
MOSI is one of the two CSPI module pins that transmit serial data. In full duplex operation, the MOSI pin
of the master CSPI module is connected to the MOSI pin of the slave CSPI module. The master CSPI
simultaneously transmits data from its MOSI pin and receives data on its MISO pin.
When enabled in the GPIO function select register the CSPI controls data direction of the MOSI pin
regardless of the state of the GPIO data direction register of the shared I/O port.
Table 28. Serial Peripheral Interface Master Control Signals
Signal
Description
Function
MOSI
Master out slave in
This bidirectional signal is the TXD output signal from the data shift
register in master mode. In slave mode, MOSI is the RXD input to the
data shift register.
This bidirectional signal is the RXD input signal to the data shift register in
master mode. In slave mode, MISO is the TXD output from the data shift
register.
This bidirectional signal is the CSPI clock output in master mode. In slave
mode, SPI_CK is an input clock signal to the CSPI.
This bidirectional signal is an output in master mode and an input in slave
mode.
This input signal is used only in master mode. It will edge or level trigger a
CSPI burst if used.
MISO
Master in slave out
SPI_CK
CSPI clock
SS_B
Slave select
DATAREADY_B
SPI ready
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC7445ARX1000LF | RISC Microprocessor Hardware Specifications |
| MC7445ARX1000LG | RISC Microprocessor Hardware Specifications |
| MC7447A | PowerPC microprocessor |
| MC7447AHX1000NB | PowerPC microprocessor |
| MC7447AHX1167NB | PowerPC microprocessor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC7220C-100M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-20C 20CORE 100M 制造商:pro-power 功能描述:CABLE, DEF 7-2-20C, 20CORE, 100M 制造商:pro-power 功能描述:CABLE, DEF 7-2-20C, 20CORE, 100M; Reel Length (Imperial):328ft; Reel Length (Metric):100m; No. of Conductors:20; Voltage Rating:440V; No. of Strands x Strand Size:7 x 0.2mm; Conductor Area CSA:0.22mm2; Jacket Colour:Black; Jacket ;RoHS Compliant: Yes |
| MC7220C-100M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-20C 20 CORE 100M |
| MC7220C-25M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-20C 20CORE 25M 制造商:pro-power 功能描述:CABLE, DEF 7-2-20C, 20CORE, 25M |
| MC7220C-25M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-20C 20 CORE 25M |
| MC7225C-25M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-25C 25CORE 25M 制造商:pro-power 功能描述:MULTICORE, 25, 7/0.2MM, 25M, BLACK 制造商:pro-power 功能描述:CABLE, DEF 7-2-25C, 25CORE, 25M 制造商:PRIVATE LABEL 功能描述:CABLE, DEF 7-2-25C, 25CORE, 25M, Reel Length (Imperial):82ft, Reel Length (Metri |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。