參數(shù)資料
型號(hào)： MC72000
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍(lán)牙無(wú)線
文件頁(yè)數(shù)： 94/156頁(yè)
文件大小： 1782K
代理商： MC72000
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94
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
Figure 61. SCR2 Register Diagram
RIE—Receive Interrupt Enable
This control bit allows interrupting the program controller. When the RIE and RE bit are set, the
program controller is interrupted when the SSI receives data. As shown in Table 42, the interrupt trigger
depends on whether the receive FIFO is enabled or not.
If the receive FIFO is disabled:
1 = An interrupt is generated when the RDR flag (in the SCSR) is set
One value can be read from the SRX register. Reading the SRX register clears the RDR bit, thus
clearing the interrupt
0 = No interrupt is generated
If the receive FIFO is enabled:
1 = An interrupt is generated when the RFF flag (in the SCSR) is set
A maximum of eight values are available to be read from the SRX register. Reading the SRX
register to remove data from the receive FIFO such that the level falls below the watermark
clears the RFF bit, thus clearing the interrupt.
0 = No interrupt is generated
Two receive data interrupts with separate interrupt vectors are available: receive data with exception
status, and receive data without exception. Table 42 shows these vectors and the conditions under which
these interrupts are generated.
Table 42. SSI Receive Data Interrupts
1
TIE—Transmit Interrupt Enable
This control bit allows interrupting the program controller. When the TIE and TE bits are set, the
program controller is interrupted when the SSI needs more transmit data. As shown in Table 43, the
interrupt trigger depends on whether the transmit FIFIO is enabled or not.
If the transmit FIFO is disabled:
1 = An interrupt is generated when the TDE flag (in the SCSR) is set
One value can be written to the STX register when this interrupt occurs.
0 = No interrupt is generated
Base + 0x06
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
RIE
TIE
RE
TE
RFEN TFEN
RXDI
R
0
TXDI
R
0
SYN
TSH-
FD
0
TSCK
P
0
SS-
IEN
0
NET
TFSI TFSL TEFS
RESET:
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
1.See
Table 37
for a complete list of interrupts.
Interrupt
RIE
Selection Control
ROE
RFEN = 0
RFEN = 1
Receive Data with Exception Status
Receive Data (without exception)
1
1
RDR = 1
RDR = 1
RFF = 1
RFF = 1
1
0
F
For More Information On This Product,
n
.
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