xii
MPC8240 Integrated Processor User's Manual
MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
6.3.7
6.3.8
6.3.8.1
6.3.9
6.3.9.1
6.3.10
6.3.10.1
6.3.11
6.3.11.1
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.6.1
6.4.7
6.4.8
6.4.9
6.4.9.1
6.4.10
6.4.10.1
6.4.11
6.4.12
6.4.13
6.4.13.1
6.4.13.2
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
FPM or EDO DRAM Page Mode Retention..................................................6-23
FPM or EDO DRAM Parity and RMW Parity...............................................6-23
RMW Parity Latency Considerations.........................................................6-24
FPM or EDO ECC..........................................................................................6-24
FPM or EDO DRAM Interface Timing with ECC.....................................6-26
FPM or EDO DRAM Refresh........................................................................6-28
FPM or EDO Refresh Timing....................................................................6-28
FPM or EDO DRAM Power Saving Modes ..................................................6-29
Self-Refresh in Sleep Mode .......................................................................6-30
SDRAM Interface Operation..............................................................................6-31
Supported SDRAM Organizations.................................................................6-35
SDRAM Address Multiplexing......................................................................6-36
SDRAM Memory Data Interface ...................................................................6-39
SDRAM ECC.................................................................................................6-41
SDRAM Burst and Single-Beat Transactions................................................6-43
SDRAM Page Mode Retention......................................................................6-44
SDRAM Paging in Sleep Mode .................................................................6-46
SDRAM Power on Initialization....................................................................6-46
MPC8240 Interface Functionality for JEDEC SDRAMs...............................6-47
SDRAM Interface Timing..............................................................................6-49
SDRAM Mode-Set Command Timing.......................................................6-53
SDRAM Parity and RMW Parity...................................................................6-53
RMW Parity Latency Considerations.........................................................6-54
SDRAM and In-Line ECC or Parity ..............................................................6-55
SDRAM Registered DIMM Mode.................................................................6-55
SDRAM Refresh ............................................................................................6-56
SDRAM Refresh Timing............................................................................6-57
SDRAM Refresh and Power Saving Modes ..............................................6-58
ROM/Flash Interface Operation.........................................................................6-61
ROM/Flash Address Multiplexing.................................................................6-65
64 or 32-Bit ROM/Flash Interface Timing.....................................................6-66
8-Bit ROM/Flash Interface Timing................................................................6-69
ROM/Flash Interface Write Operations .........................................................6-70
ROM/Flash Interface Write Timing...............................................................6-71
Port X Interface ..............................................................................................6-72
Chapter 7
Central Control Unit
7.1
7.1.1
7.1.2
Internal Buffers.....................................................................................................7-1
Processor Core/System Memory Buffers.........................................................7-3
Processor/PCI Buffers......................................................................................7-4