MOTOROLA
Illustrations
xxi
ILLUSTRATIONS
Figure
Number
Title
Page
Number
1-1
1-2
1-3
1-4
1-5
1-6
2-1
2-2
2-3
2-4
2-5
2-6
3-1
3-2
3-3
3-4
3-5
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
5-1
5-2
5-3
5-4
5-5
5-6
5-7
MPC8240 Integrated Processor Functional Block Diagram................................1-2
System Using an Integrated MPC8240 as a Host Processor................................1-5
Embedded System Using an MPC8240 as a Distributed Processor....................1-6
Embedded System Using an MPC8240 as a Peripheral Processor......................1-7
MPC8240 Integrated Processor Core Block Diagram.........................................1-9
MPC8240 Peripheral Logic Block Diagram......................................................1-11
MPC8240 Integrated Processor Core Block Diagram.........................................2-2
MPC8240 Programming ModelRegisters......................................................2-12
Hardware Implementation Register 0 (HID0) ...................................................2-13
Hardware Implementation Register 1 (HID1) ...................................................2-17
Hardware Implementation-Dependent Register 2 (HID2).................................2-17
Data Cache Organization...................................................................................2-22
MPC8240 Signal Groupings................................................................................3-3
Clock Subsystem Block Diagram......................................................................3-32
Timing Diagram (1X, 1.5X, 2X, 2.5X, and 3X examples)................................3-33
Clocking SolutionSmall Load Requirements.................................................3-35
Clocking SolutionHigh Clock Fanout Required............................................3-35
Processor Core Address Map A...........................................................................4-3
PCI Master Memory Address Map A..................................................................4-4
PCI Master I/O Address Map A...........................................................................4-5
Address Map B in Host Mode .............................................................................4-9
Inbound PCI Address Translation......................................................................4-10
Outbound PCI Address Translation...................................................................4-12
Local Memory Base Address Register (LMBAR)0x10.................................4-13
Inbound Translation Window Register (ITWR)................................................4-14
Outbound Memory Base Address Register (OMBAR)0x0_2300.................4-15
Outbound Translation Window Register (OTWR)0x0_2308........................4-16
Embedded Utilities Memory Block Mapping to Local Memory.......................4-17
Embedded Utilities Memory Block Mapping to PCI Memory..........................4-18
Processor Accessible Configuration Space..........................................................5-6
PCI Accessible Configuration Space...................................................................5-7
PCI Command Register.....................................................................................5-10
PCI Status Register............................................................................................5-11
Power Management Configuration Register 1 (PMCR1)..................................5-16
Power Management Configuration Register 2 (PMCR2)..................................5-17
Processor Interface Configuration Register 1 (PICR1)0xA8.........................5-22