MOTOROLA
Illustrations
xxv
ILLUSTRATIONS
Figure
Number
Title
Page
Number
11-3
11-4
11-5
11-6
11-7
11-8
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-10
12-11
12-12
12-13
12-14
12-15
12-16
12-17
12-18
12-19
13-1
14-1
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
I
2
C Address Register (I2CADR).......................................................................11-8
I
2
C Frequency Divider Register (I2CFDR).......................................................11-8
I
2
C Control Register (I2CCR).........................................................................11-10
I
2
C Status Register (I2CSR)............................................................................11-12
I
2
C Data Register (I2CDR)..............................................................................11-13
Example I
2
C Interrupt Service Routine Flowchart..........................................11-18
EPIC Unit Block Diagram.................................................................................12-3
EPIC Interrupt Generation Block DiagramNon-programmable Registers....12-8
Serial Interrupt Interface Protocol ...................................................................12-12
Feature Reporting Register (FRR)...................................................................12-15
Global Configuration Register (GCR).............................................................12-15
EPIC Interrupt Configuration Register (EICR) ...............................................12-16
EPIC Vendor Identification Register (EVI).....................................................12-17
Processor Initialization Register (PI)...............................................................12-18
Spurious Vector Register (SVR)......................................................................12-18
Timer Frequency Reporting Register (TFRR).................................................12-19
Global Timer Current Count Register (GTCCR).............................................12-20
Global Timer Base Count Register (GTBCR).................................................12-20
Global Timer Vector/Priority Register (GTVPR)............................................12-21
Global Timer Destination Register (GTDR)....................................................12-22
Direct and Serial Interrupt Vector/Priority Registers (IVPR and SVPR)........12-23
Direct and Serial Destination Registers (IDR and SDR).................................12-24
Processor Current Task Priority Register (PCTPR).........................................12-25
Processor Interrupt Acknowledge Register (IACK)........................................12-26
Processor End of Interrupt Register (EOI).......................................................12-26
Internal Error Management Block Diagram......................................................13-2
MPC8240 Peripheral Logic Power States..........................................................14-7
Example PCI Address Attribute Signal Timing for Burst Read Operations .....15-3
Example PCI Address Attribute Signal Timing for Burst Write Operations.....15-4
64-Bit Mode, DRAM and SDRAM Physical Address for Debug.....................15-5
32-Bit Mode, DRAM and SDRAM Physical Address for Debug.....................15-5
64-Bit Mode, ROM and Flash Physical Address for Debug .............................15-6
32-Bit Mode, ROM and Flash Physical Address for Debug .............................15-6
8-bit mode, ROM and FLASH Physical Address for Debug.............................15-6
Example FPM Debug Address, MIV, and MAA Timings for Burst Read
Operation..........................................................................................................15-8
Example FPM Debug Address, MIV, and MAA Timings for Burst Write
Operation..........................................................................................................15-9
Example EDO Debug Address, MIV, and MAA Timings for Burst Read
Operation........................................................................................................15-10
Example EDO Debug Address, MIV, and MAA Timings for Burst Write
Operation........................................................................................................15-11
15-9
15-10
15-11