viii
MPC8240 Integrated Processor User's Manual
MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
3.2.1.9
3.2.1.9.1
3.2.1.9.2
3.2.1.10
3.2.1.10.1
3.2.1.10.2
3.2.1.11
3.2.1.11.1
3.2.1.11.2
3.2.1.12
3.2.1.12.1
3.2.1.12.2
3.2.1.13
3.2.1.13.1
3.2.1.13.2
3.2.1.14
3.2.1.15
3.2.2
3.2.2.1
3.2.2.2
3.2.2.3
3.2.2.4
3.2.2.5
3.2.2.6
3.2.2.7
3.2.2.8
3.2.2.9
3.2.2.10
3.2.2.10.1
3.2.2.10.2
3.2.2.11
3.2.2.11.1
3.2.2.11.2
3.2.2.12
3.2.2.13
3.2.2.14
3.2.2.15
3.2.2.16
3.2.2.17
3.2.2.18
3.2.2.19
3.2.3
3.2.3.1
Parity (PAR)...............................................................................................3-13
Parity (PAR)Output............................................................................3-13
Parity (PAR)Input ..............................................................................3-13
Parity Error (PERR) ...................................................................................3-13
Parity Error (PERR)Output................................................................3-13
Parity Error (PERR)Input...................................................................3-13
System Error (SERR).................................................................................3-13
System Error (SERR)Output..............................................................3-14
System Error (SERR)Input.................................................................3-14
Stop (STOP) ...............................................................................................3-14
Stop (STOP)Output............................................................................3-14
Stop (STOP)Input...............................................................................3-14
Target Ready (TRDY)................................................................................3-14
Target Ready (TRDY)Output.............................................................3-14
Target Ready (TRDY)Input................................................................3-15
Interrupt Request (INTA)Output............................................................3-15
ID Select (IDSEL)Input..........................................................................3-15
Memory Interface Signals ..............................................................................3-16
Row Address Strobe (RAS[0D7])Output................................................3-16
Column Address Strobe (CAS[0D7])Output ..........................................3-16
SDRAM Command Select (CS[0D7])Output.........................................3-16
SDRAM Data Qualifier (DQM[0D7])Output.........................................3-17
Write Enable (WE)Output......................................................................3-17
SDRAM Address (SDMA[11D0])Output...............................................3-17
SDRAM Address 12 (SDMA12)Output ................................................3-18
SDRAM Internal Bank Select 1 (SDBA1)Output..................................3-18
SDRAM Internal Bank Select 0 (SDBA0)Output..................................3-18
Data Bus (DH[0D31], DL[0D31])...............................................................3-18
Data Bus (DH[0D31], DL[0D31])Output............................................3-19
Data Bus (DH[0D31], DL[0D31])Input...............................................3-19
Data Parity/ECC (PAR[0D7]).....................................................................3-19
Data Parity (PAR[0D7])Output...........................................................3-19
Data Parity (PAR[0D7])Input.............................................................3-20
ROM Address 19D12 (AR[19D12])Output.............................................3-20
SDRAM Clock Enable (CKE)Output ....................................................3-20
SDRAM Row Address Strobe (SDRAS)Output....................................3-21
SDRAM Column Address Strobe (SDCAS)Output...............................3-21
ROM Bank 0 Select (RCS0)Output .......................................................3-21
ROM Bank 1 Select (RCS1)Output .......................................................3-21
Flash Output Enable (FOE)Output.........................................................3-22
Address Strobe (AS)Output....................................................................3-22
EPIC Control Signals .....................................................................................3-22
Discrete Interrupt 0D4 (IRQ[0-4])Input..................................................3-22