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MPC8240 Integrated Processor User's Manual
MOTOROLA
ILLUSTRATIONS
Figure
Number
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5-9
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Title
Page
Number
Processor Interface Configuration Register 2 (PICR2)0xAC........................5-24
ECC Single-Bit Error Counter Register0xB8................................................5-26
ECC Single-Bit Error Trigger Register0xB9.................................................5-27
Error Enabling Register 1 (ErrEnR1)0xC0....................................................5-27
Error Enabling Register 2 (ErrEnR2)0xC4....................................................5-28
Error Detection Register 1 (ErrDR1)0xC1....................................................5-30
Error Detection Register 2 (ErrDR2)0xC5....................................................5-31
Internal Processor Bus Error Status Register0xC3........................................5-31
PCI Bus Error Status Register0xC7...............................................................5-32
Processor/PCI Error Address Register0xC8..................................................5-32
Address Map B Options Register (AMBOR)0xE0........................................5-33
Memory Starting Address Register 10x80.....................................................5-35
Memory Starting Address Register 20x84.....................................................5-35
Extended Memory Starting Address Register 10x88.....................................5-36
Extended Memory Starting Address Register 20x8C....................................5-36
Memory Ending Address Register 10x90......................................................5-37
Memory Ending Address Register 20x94......................................................5-37
Extended Memory Ending Address Register 10x98......................................5-38
Extended Memory Ending Address Register 20x9C.....................................5-38
Memory Bank Enable Register0xA0.............................................................5-39
Memory Page Mode Register0xA3 ...............................................................5-40
Memory Control Configuration Register 1 (MCCR1)0xF0..........................5-41
Memory Control Configuration Register 2 (MCCR2)0xF4..........................5-44
Memory Control Configuration Register 3 (MCCR3)0xF8..........................5-46
Memory Control Configuration Register 4 (MCCR4)0xFC..........................5-49
Block Diagram for Memory Interface .................................................................6-3
FPM or EDO DRAM Memory Interface Block Diagram ...................................6-6
Example 16-Mbyte DRAM System with Parity64-Bit Mode..........................6-8
DRAM Memory Organization.............................................................................6-9
DRAM Address Multiplexing SDMA[12D0]32 Bit Mode............................6-13
DRAM Address Multiplexing SDMA[12D0]64 Bit Mode............................6-14
FPM-EDO Flow-through Memory Interface.....................................................6-16
DRAM Single-Beat Read Timing (No ECC)....................................................6-19
DRAM Four-Beat Burst Read Timing (No ECC)64-Bit Mode.....................6-19
DRAM Eight-Beat Burst Read Timing Configuration32-Bit Mode..............6-20
DRAM Single-Beat Write Timing (No ECC) ...................................................6-21
DRAM Four-Beat Burst Write Timing (No ECC)64-Bit Mode....................6-21
DRAM Eight-beat Burst Write Timing (No ECC)32 Bit Mode....................6-22
FPM DRAM Burst Read with ECC...................................................................6-27
EDO DRAM Burst Read Timing with ECC......................................................6-27
DRAM Single-Beat Write Timing with RMW or ECC Enabled ......................6-28
DRAM Bank Staggered CBR Refresh Timing Configuration ..........................6-29
DRAM Self-Refresh Timing Configuration......................................................6-30