MOTOROLA
Contents
xiii
CONTENTS
Paragraph
Number
Title
Page
Number
7.1.2.1
7.1.2.2
7.1.3
7.1.3.1
7.1.3.2
7.1.3.3
7.1.3.4
7.2
Processor-to-PCI-Read Buffer (PRPRB).....................................................7-4
Processor-to-PCI-Write Buffers (PRPWBs)................................................7-5
PCI/System Memory Buffers...........................................................................7-6
PCI to System Memory Read Buffering......................................................7-7
PCI-to-System-Memory-Read Buffers (PCMRBs).....................................7-7
Speculative PCI Reads from System Memory.............................................7-8
PCI-to-System-Memory-Write Buffers (PCMWBs)...................................7-8
Internal Arbitration...............................................................................................7-9
Chapter 8
PCI Bus Interface
8.1
8.1.1
8.1.2
8.1.3
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.3
8.3.1
8.3.2
8.3.3
8.3.3.1
8.3.3.2
8.3.3.3
8.3.4
8.3.5
8.3.6
8.4
8.4.1
8.4.2
8.4.3
8.4.3.1
8.4.3.2
8.4.4
8.4.5
8.4.5.1
8.4.5.2
PCI Interface Overview........................................................................................8-1
The MPC8240 as a PCI Initiator......................................................................8-2
The MPC8240 as a PCI Target ........................................................................8-3
PCI Signal Output Hold Timing ......................................................................8-3
PCI Bus Arbitration..............................................................................................8-4
PCI Bus Arbiter Operation...............................................................................8-4
PCI Bus Parking...............................................................................................8-6
Broken Master Lock-Out .................................................................................8-6
Bus Lock Mode................................................................................................8-6
Power-Saving Modes and the PCI Arbiter.......................................................8-6
PCI Bus Protocol..................................................................................................8-7
Basic Transfer Control.....................................................................................8-7
PCI Bus Commands.........................................................................................8-8
Addressing........................................................................................................8-9
Memory Space Addressing........................................................................8-10
I/O Space Addressing.................................................................................8-10
Configuration Space Addressing ...............................................................8-10
Device Selection.............................................................................................8-10
Byte Alignment..............................................................................................8-11
Bus Driving and Turnaround .........................................................................8-11
PCI Bus Transactions.........................................................................................8-12
Read Transactions..........................................................................................8-12
Write Transactions.........................................................................................8-13
Transaction Termination................................................................................8-14
Master-Initiated Termination.....................................................................8-14
Target-Initiated Termination......................................................................8-15
Fast Back-to-Back Transactions ....................................................................8-17
Configuration Cycles .....................................................................................8-18
The PCI Configuration Space Header........................................................8-18
Accessing the PCI Configuration Space....................................................8-19