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MPC8240 Integrated Processor User's Manual
MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
15.3
15.3.1
15.4
15.4.1
15.4.2
15.4.2.1
15.4.2.2
15.4.2.3
15.4.3
15.4.3.1
15.4.3.2
15.4.3.3
15.5
15.5.1
15.5.2
15.5.2.1
15.5.2.2
15.5.2.3
15.5.2.4
Memory Interface Valid (MIV)..........................................................................15-7
MIV Signal Timing ........................................................................................15-8
Memory Datapath Error Injection/Capture.......................................................15-16
Memory Data Path Diagnostic Registers Address Map...............................15-16
Memory Data Path Error Injection Mask Registers.....................................15-17
Data High Error Injection Mask Register.................................................15-18
Data Low Error Injection Mask Register.................................................15-18
Parity Error Injection Mask Register........................................................15-19
Memory Data Path Error Capture Monitor Registers...................................15-19
Data High Error Capture Monitor Register..............................................15-20
Data Low Error Capture Monitor Register...............................................15-20
Parity Error Capture Monitor Register.....................................................15-20
JTAG/Testing Support......................................................................................15-21
JTAG Signals................................................................................................15-22
JTAG Registers and Scan Chains.................................................................15-22
Bypass Register........................................................................................15-22
Boundary-Scan Registers.........................................................................15-23
Instruction Register ..................................................................................15-23
TAP Controller.........................................................................................15-23
Appendix A
PowerPC Instruction Set Listings
A.1
A.2
A.3
A.4
A.5
Instructions Sorted by Mnemonic........................................................................A-1
Instructions Sorted by Opcode ............................................................................A-9
Instructions Grouped by Functional Categories................................................A-17
Instructions Sorted by Form..............................................................................A-27
Instruction Set Legend.......................................................................................A-38
Appendix B
Bit and Byte Ordering
B.1
B.2
B.3
B.4
B.4.1
B.5
Byte Ordering Overview .....................................................................................B-1
Byte-Ordering Mechanisms.................................................................................B-1
Big-Endian Mode ................................................................................................B-2
Little-Endian Mode..............................................................................................B-6
I/O Addressing in Little-Endian Mode..........................................................B-15
Setting the Endian Mode Of Operation.............................................................B-15