MOTOROLA
Tables
xxix
TABLES
Table
Number
Title
Page
Number
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
7-1
7-2
8-1
8-2
8-3
8-4
8-5
8-6
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
FPM or EDO System Configurations................................................................6-15
Memory Interface Configuration Register Fields..............................................6-16
FPM or EDO Timing Parameters ......................................................................6-18
The MPC8240 FPM or EDO ECC Syndrome Encoding (Data bits 0D31)........6-25
The MPC8240 FPM or EDO ECC Syndrome Encoding (Data bits 32D63)......6-25
FPM or EDO DRAM Power Saving Modes Refresh Configuration.................6-29
Unsupported Multiplexed Row and Column Address Bits................................6-35
Supported SDRAM Device Configurations64-bit Mode...............................6-36
Bit Name and Location Cross-listing.................................................................6-39
SDRAM System Configurations........................................................................6-40
The MPC8240 SDRAM ECC Syndrome Encoding (Data Bits 0D31) ..............6-43
The MPC8240 SDRAM ECC Syndrome Encoding (Data Bits 32D63) ............6-43
MPC8240 SDRAM Interface Command and Data Inputs.................................6-49
SDRAM Interface Timing Intervals ..................................................................6-50
SDRAM Controller Power Saving Configurations............................................6-59
SDRAM Power Saving Modes Refresh Configuration.....................................6-59
Reset Configurations of ROM/Flash Controller................................................6-64
Snooping Behavior Caused by a Hit in an Internal Buffer..................................7-7
Internal Arbitration Priorities...............................................................................7-9
PCI Bus Commands.............................................................................................8-8
PCI Configuration Space Header Summary......................................................8-19
CONFIG_ADDR Register Fields......................................................................8-20
Type 0 ConfigurationDevice Number to IDSEL Translation........................8-22
Special-Cycle Message Encodings....................................................................8-26
Initialization Options for PCI Controller...........................................................8-30
DMA Register Summary.....................................................................................9-2
DMA Descriptor Summary..................................................................................9-9
DMR Field Descriptions0x100......................................................................9-12
DSR Field Descriptions0x104.......................................................................9-15
CDAR Field Descriptions0x108....................................................................9-16
SAR Field Description0x110.........................................................................9-17
DAR Field Description0x118........................................................................9-17
BCR Field Descriptions0x120.......................................................................9-18
NDAR Field Descriptions0x124....................................................................9-19
Message Register Summary...............................................................................10-2
Doorbell Register Summary ..............................................................................10-2
IMR and OMR Field Descriptions Offset 0x050D0x05C..............................10-2
IDBR Field Descriptions Offset 0x068..........................................................10-3
ODBR Field Descriptions Offset 0x060........................................................10-4
I
2
O PCI Configuration Identification Register Settings....................................10-4
I
2
O Register Summary.......................................................................................10-5
Queue Starting Address.....................................................................................10-6
OMISR Field Descriptions Offset 0x030 ......................................................10-9