參數(shù)資料
型號： PSD813FH
英文描述： Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器)
中文描述： 場可編程微控制器外圍設(shè)備與快閃記憶體（帶閃存的現(xiàn)場可編程微控制器）
文件頁數(shù)： 2/83頁
文件大?。?/td> 369K
代理商： PSD813FH
PSD813FN/FH
Prelimnary
2
J
Low V
CC
write inhibit <= 3.2 V for the Flash Memory.
J
Guaranteed Minimum 10,000 Erase/Write Cycles.
J
A simple, programmable interface to 8-bit microcontrollers using either multiplexed
or non-multiplexed busses. The bus interface logic directly decodes microcontroller
control signals. Supports all popular microcontrollers.
J
Three Flexible OTP PLD Sections
One PLD is used for internal PSD address decoding, one is used for external device
address decoding, and one is used as a general-purpose design resource. The
general-purpose PLD may be used to efficiently implement a variety of logic functions
commonly associated with MCUs such as state machines, address decoders, address
generators, serial channels, multiprocessor mailboxes, and shift registers.
The general-purpose PLD also supports 12-Output Micro
Cells and 23-Input
Micro
Cells. The MCM PSD813FN/FH dedicates seven Output and eight Input
Micro
Cells to Flash memory usage and SRAM standby voltage control. Although
the seven Output Micro
Cells are dedicated, an internal product term allocator
redistributes any unused product terms if needed by the remaining Micro
Cells.
J
Internal 4Kbit SRAM. The SRAM retains data if power is lost by automatically
switching to an external standby power source.
J
Nineteen individually configurable I/O Port Pins. The Ports may be used as
microcontroller I/Os, PLD I/Os, latched microcontroller address outputs or special
function I/Os.
J
The programmable Power Management Unit (PMU) supports two separate, low-power
modes allowing operations with as little as 25μA (at 5V V
CC
). The device can
automatically detect a lack of microcontroller activity and put the PSD into power down
mode.
J
Page Logic
Page Logic is connected to the ZPLDs and enables address space expansion for
microcontrollers with limited address space capability. Up to 16 pages are available.
J
Security Bit
The security bit prevents reading the PSD configuration, ZPLD, EPROM Boot array,
and Flash memory contents. This inhibits copying the device on a programmer.
J
Development Tools
Supported by the PSDsoft
TM
MS-Windows
compatible development tools. Includes
PSDabel as the design entry method, an efficient Fitter, and an Address Translator
(see Figure 2).
J
Packaging consists of a 52 pin plastic chip carrier.
Key Features
(cont.)
Please refer to the revision block at
the end of this document for updated
information.
相關(guān)PDF資料
PDF描述
PSD82 Three Phase Rectifier Bridges
PSD834F2V Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM(2M位+256K位雙路閃速存儲器和64K位靜態(tài)RAM,閃速PSD,3.3V電源,用于8位MCU.)
PSD834F2 Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的閃速ISP外圍)
PSD835G2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(8位微控制器片上存儲器可編程外設(shè))
PSD835G2 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-254AA Tabless package; Similar to IRHMJ57160 with optional Total Dose Rating of 1000kRads
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD813FH-15J 制造商:WSI 功能描述:
PSD813FH-90J 制造商:WSI 功能描述:
PSD813FN-15J 制造商:WSI 功能描述:
PSD833F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD833F2-90JI 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*