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參數(shù)資料
| 型號： | PSD813FH |
| 英文描述： | Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器) |
| 中文描述： | 場可編程微控制器外圍設(shè)備與快閃記憶體（帶閃存的現(xiàn)場可編程微控制器） |
| 文件頁數(shù)： | 43/83頁 |
| 文件大?。?/td> | 369K |
| 代理商： | PSD813FH |
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Prelimnary
PSD813FN/FH
43
Memory Blocks
(cont.)
Memory Select for 8031 Microcontrollers
(cont.)
Mixed Mode is another mode of operation that is not set by the MCU at Run-Time
but is set by an NVM bit from the PSD device programming file that PSDsoft creates. This
mode deals with overlapping Boot EPROM addresses such as when two PSD Boot
EPROM blocks start at address 8000, but one is in program space and the other is in data
space.
J
Mixed Mode
This mode allows individual Boot EPROM blocks with overlapping addresses to be
configured in either program space or data space. The CSBOOTx chip select
equations for the overlapping blocks must be qualified with the 8031 RD input. An
active low RD will select Boot EPROM blocks in data space and disable the blocks in
program space. The NVM bit is automatically set by PSDsoft if the keyword RD is used
in any CSBOOTx equation. This NVM bit is equivalent to setting Bit 1 in the VM
register, only it is there from system power-up. Here are some example CSBOOTx
equations:
CSBOOT0 = address >= ^h8000 & address <= ^h1FFF & RD; “resides program space
CSBOOT1 = address >= ^h8000 & address <= ^h1FFF & !RD; “resides data space
There are two reasons to use this mode. First, this mode must be used if PSD Boot
EPROM addresses overlap each other but reside in different spaces. Second, this mode
can be used if PSD Boot EPROM block addresses do not overlap but it is desired to have
one or more Boot EPROM blocks reside in data space and the designer wants this to be set
in NVM configuration from power up (not set at Run-Time). IMPORTANT: For Boot EPROM
blocks that reside in data space, the access time is calculated from RD valid to data valid.
The designer must ensure that EPROM access time is sufficient for the system, or else use
the VM register bit 1 without overlapping addresses.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD813FH-15J | 制造商:WSI 功能描述: |
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| PSD833F2-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD833F2-90JI | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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