參數(shù)資料
型號： PSD813FH
英文描述： Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器)
中文描述： 場可編程微控制器外圍設(shè)備與快閃記憶體（帶閃存的現(xiàn)場可編程微控制器）
文件頁數(shù)： 77/83頁
文件大?。?/td> 369K
代理商： PSD813FH
Prelimnary
PSD813FN/FH
77
Device Operation
(cont.)
Memory Sectors
The sectors of the Flash Memory are shown in Figure 1. The memory array is divided into
8 sectors of 64K bytes. Each sector can be erased separately or any combination of sectors
can be erased simultaneously. The Sector Erase operation is managed automatically by the
P/E.C. The operation can be suspended in order to read from any another sector, and then
resumed.
Operations
Operations are defined as specific bus cycles and signals which allow Memory Read,
Command Write, Output Disable, Standby, Read Status Bits, and Electronic Signature
Read. They are shown in Tables 1 and 2.
J
Read
Read operations are used to output the contents of the Memory Array, the Status
Register or the Electronic Signature. Both Chip Enable CSF and Output Enable RDF
must be low in order to read the output of the memory. The Chip Enable input also
provides power control and should be used for device selection. Output Enable should
be used to gate data onto the output independent of the device selection. The data
read depends on the previous command written to the memory (see instructions RST
and RSIG, and Status Bits).
J
Write
Write operations are used to give Instruction Commands to the memory or to latch
input data to be programmed. A write operation is initiated when Chip Enable CSF is
Low and Write Enable WRF is Low with Output Enable RDF High. Addresses are
latched on the falling edge of WRF or CSF whichever occurs last. Commands and
Input Data are latched on the rising edge of WRF or CSF whichever occurs first.
J
Output Dsable
The data outputs are high impedance when the Output Enable RDF is High with Write
Enable WRF High.
J
Standby
The memory is in standby when Chip Enable CSF is High and Program/Erase Controller
P/E.C. is Idle. The power consumption is reduced to the standby level and the outputs
are high impedance, independent of the Output Enable RDF or Write Enable WRF
inputs.
J
Automatic Standby
After 150 ns of inactivity and when CMOS levels are driving the addresses, the chip
automatically enters a pseudo standby mode where power consumption is reduced to
the CMOS standby value, while outputs are still driving the bus.
Appendix A –
Flash Memory
(cont.)
相關(guān)PDF資料
PDF描述
PSD82 Three Phase Rectifier Bridges
PSD834F2V Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM(2M位+256K位雙路閃速存儲器和64K位靜態(tài)RAM,閃速PSD,3.3V電源,用于8位MCU.)
PSD834F2 Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的閃速ISP外圍)
PSD835G2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(8位微控制器片上存儲器可編程外設(shè))
PSD835G2 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-254AA Tabless package; Similar to IRHMJ57160 with optional Total Dose Rating of 1000kRads
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD813FH-15J 制造商:WSI 功能描述:
PSD813FH-90J 制造商:WSI 功能描述:
PSD813FN-15J 制造商:WSI 功能描述:
PSD833F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD833F2-90JI 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*