參數(shù)資料
型號(hào)： PSD813FH
英文描述： Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場(chǎng)可編程微控制器)
中文描述： 場(chǎng)可編程微控制器外圍設(shè)備與快閃記憶體（帶閃存的現(xiàn)場(chǎng)可編程微控制器）
文件頁(yè)數(shù)： 32/83頁(yè)
文件大小： 369K
代理商： PSD813FH
PSD813FN/FH
Prelimnary
32
I/OPorts
(cont.)
Port Registers
Each port has a set of registers used for configuration (PCR, Port Configuration Registers)
and data transfers (PDR, Port Data Registers). The contents of the registers can be
accessed by the microcontroller through normal read/write bus cycles at the addresses
given in Table 22. The address of the registers is comprised by that of the CSIOP output
from the DPLD plus an address offset as listed in the tables.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, Bit 0 in a register refers to Bit 0 in its port. The three Port
Configuration Registers, shown in Table 18, are used for setting the port configuration. Each
register is set to zero at power up.
Register Name
Port
MCUAccess
Control
Direction
Drive*
A,B
A,B,C,D
A,B,C,D
Write/Read
Write/Read
Write/Read
Table 18. Port Configuration Registers
*
Note: See Table 20 for Drive Register bit definition.
Control Register
A “0” in the Control Register sets the Port pin to MCU I/O for Port A and B. A “1” sets the
Port pin to Address Out mode. The default mode is MCU I/O.
Drection Register
Controls the direction of data flow in the I/O Ports. A “1” configures the port to be an
output, and a “0” to an input. The I/O configuration can be read from the Direction Register.
The default mode is input.
As shown in Figure 12, the direction of data flow in Port A,B and C pins are also controlled
by the output enable (.oe) product term from the GPLD AND array. If the .oe product term is
not active, the Direction Register has sole control of the pin direction.
An example of a configuration for a port with the three least significant bits set to output and
the remainder set to input is shown in Table 19. The Port D register has only the three least
significant bits active.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
1
1
Table 19. Port Drection Assignment Example
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PSD833F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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