參數(shù)資料
型號： PSD813FH
英文描述： Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器)
中文描述： 場可編程微控制器外圍設備與快閃記憶體（帶閃存的現(xiàn)場可編程微控制器）
文件頁數(shù)： 46/83頁
文件大?。?/td> 369K
代理商： PSD813FH
PSD813FN/FH
Prelimnary
46
Power
Management
Unit
(cont.)
PLD
Access
Recovery Time
to Normal
Access
PLD
Recovery Time
to Normal
Operation
Propagation
Delay
Access
Time
Mode
Power Down
Normal tpd
(Note 1)
0
No Access
tLVDV
Sleep
t
PD4
(Note 2)
t
PD5
(Note 3)
No Access
tLVDV1
Table 27. Summary of PSD813FN/FHTimng and Standby Current During
Power Down and Sleep Mode
NOTES:
1. Power Down does not affect the operation of the PLD.
2. In Sleep Mode any input to the PLD will have a propagation delay of t
PD4
.
3. PLD recovery time to normal operation after existing Sleep Mode. An input to the PLD during the
transition will have a propagation delay of t
PD5
.
CMiser Bit
The CMiser function reduces DC power consumption of the Boot EPROM and SRAM and
is independent of APD logic. When CMiser is enabled, the lowest level of DC power is
consumed, however, Boot EPROM and SRAM access times will be extended an
additional 10 ns. See the PSD DC Characteristics and MCU read timing specifications in
this document for more details.
The CSI Input
Pin PD2 of Port D can be configured in PSDsoft as the PSD chip select input CSI.
If configured as such, the CSI pin will invoke Power Down mode (as described above)
when its level is a logical one. When CSI is logic zero, the PSD functions normally. The CSI
function is independent of any Run-Time power saving options. If Power Down mode is
activated from CSI, exit from this mode is identical to Power Down mode activated by the
APD logic.
Input Clock
If the PSD is configured to use the CLKIN pin (Port D PD1) for use in the PLD AND array
and Output MicroCells, this clock signal may be disabled during Power Down mode to
further reduce power consumption. This feature is enabled by the MCU and Run-Time
using the PMMR0 register as shown in Table 28. Note that even when the clock signal
CLKIN is blocked by this feature, the clock signal is still active at the APD down-counter.
SRAM Standby Mode
The PSD SRAM has a dedicated VSTBY pin (Port C PC2) that can be connected to an
external battery. When system V
CC
falls below the battery voltage at the VSTBY pin, the
PSD will automatically connect VSTBY as the power source for the PSD SRAM. The SRAM
standby current (I
STBY
) is typically 0.5 μA and the minimum data retention voltage is 2.0
volts. Note: Pin PC2 should be grounded if not used as VSTBY.
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相關代理商/技術參數(shù)
參數(shù)描述
PSD813FH-15J 制造商:WSI 功能描述:
PSD813FH-90J 制造商:WSI 功能描述:
PSD813FN-15J 制造商:WSI 功能描述:
PSD833F2-90J 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD833F2-90JI 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
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