參數(shù)資料
型號(hào)： PSD813FH
英文描述： Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場(chǎng)可編程微控制器)
中文描述： 場(chǎng)可編程微控制器外圍設(shè)備與快閃記憶體（帶閃存的現(xiàn)場(chǎng)可編程微控制器）
文件頁(yè)數(shù)： 74/83頁(yè)
文件大?。?/td> 369K
代理商： PSD813FH
PSD813FN/FH
Prelimnary
74
Operation
CSF
RDF
WRF
D0 – D7
Read
V
IL
V
IL
V
IL
V
IH
V
IL
V
IH
V
IH
X
V
IH
V
IL
V
IH
X
Data Output
Write
Data Input
Output Disable
Hi-Z
Standby
Hi-Z
Appendix A –
Flash Memory
(cont.)
Operation
CSF
RDF WRF
A0
A1
A6
Addresses
D0 – D7
Manufact. Code
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
V
IH
V
IL
V
IL
V
IL
V
IL
Don’t Care
20h
Device Code
Don’t Care
0E2h
Table 1. Operations
Table 2. Electronic Signature
NOTE:
See RSIG instruction
Device Operation
Signal Descriptions
J
A0 – A18 Address Inputs
The Address inputs for the memory array are latched during a write operation.
When A0, A1 and A6 are Low, the Electronic Signature Manufacturer code is read.
When A0 is High and A1 and A6 are Low, the Device code is read. See the RSIG
instruction and Table 2.
J
D0 – D7 Data Input/Outputs
The data input is a byte to be programmed or a command written to the C.I. Both are
latched when Chip Enable CSF and Write Enable WRF are active. The data output is
from the memory Array, the Electronic Signature, the Data Polling bit (D7), the Toggle
Bit (D6), the Error bit (D5) or the Erase Timer bit (D3). Outputs are valid when Chip
Enable CSF and Output Enable RDF are active. The output is high impedance when
the chip is deselected or the outputs are disabled.
J
CSF Chip Enable
The Chip Enable activates the memory control logic, input buffers, decoders and sense
amplifiers. CSF High deselects the memory and reduces the power consumption to the
standby level. CSF can also be used to control writing to the command register and to
the memory array, while WRF remains at a low level. Addresses are then latched on
the falling edge of CSF while data is latched on the rising edge of CSF.
J
RDF Output Enable
The Output Enable gates the outputs through the data buffers during a read operation.
J
WRF Write Enable
This input controls writing to the Command Register and Address and Data latches.
Addresses are latched on the falling edge of WRF, and Data Inputs are latched on the
rising edge of WRF.
J
V
CC
Supply Voltage
The power supply for all operations (Read, Program and Erase).
J
V
SS
Ground
V
SS
is the reference for all voltage measurements.
NOTE:
X = V
IL
or V
IH
.
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PSD813FH-90J 制造商:WSI 功能描述:
PSD813FN-15J 制造商:WSI 功能描述:
PSD833F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD833F2-90JI 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
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