- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368232 > PSD813FH Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器) PDF資料下載
參數(shù)資料
| 型號(hào)： | PSD813FH |
| 英文描述： | Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器) |
| 中文描述： | 場可編程微控制器外圍設(shè)備與快閃記憶體（帶閃存的現(xiàn)場可編程微控制器） |
| 文件頁數(shù)： | 40/83頁 |
| 文件大?。?/td> | 369K |
| 代理商： | PSD813FH |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當(dāng)前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁
PSD813FN/FH
Prelimnary
40
Memory
Block
The PSD813FN/FH are a multi-chip module that includes a PSD6XX die and a 4 megabit
Flash memory die configured to operate as a 1 Mb device. The PSD813FN/FH includes
32 Kbytes of OTP Boot EPROM; the Flash die provides 128 Kbytes of Flash memory.
The OTP Boot EPROM is used for system boot up and for storing the Flash memory
programming algorithm. The Flash erase and programming algorithms are compatible to
the AMD and SGS-Thomson Embedded Erase and Programming Algorithm
TM
. The Flash
memory can be erased or programmed while the microcontroller is executing code from the
Boot EPROM.
Chip selects for the memory blocks come from the DPLD and GPLD decoding logic and are
defined by the user in the PSDsoft software. Figure 17 shows the organization of the
Memory Block.
Boot EPROM
The chip selects (CSBOOT0–3) for the OTP Boot EPROM are generated from the DPLD
address decoder. The CSBOOT0–3 are defined in 8 Kbyte boundaries and should not
overlap the Flash memory address space.
Flash Memory
The Flash die that is used on this MCM is a 4 Mbit Flash device but only 1 Mbit will be
addressed. Address lines A14 and A15 are inactive during Flash reads. This leaves
address lines A16, A17, and A18 to page through eight 16 Kbyte sectors of Flash memory.
Each 16 Kbyte sector of Flash is addressed by the address lines A0–A13. This Flash
paging is simplified by the configuration of the DPLD and the GPLD. FS0–7 are the chip
selects for each block that is defined in the DPLD at 16 Kbyte boundaries. The designer
may custom configure Flash addressing schemes by the HDL equations developed in
PSDsoft. The use of the internal PSD Page register is very effective in this application.
See Figure 17 and Table 24.
NOTE:
Unlike Flash reads, whenever the embedded Flash algorithms are exercised
(write, erase, ID, etc), address line A14 to the Flash is enabled (as configured by
the HDL) to pass commands from the MCU to the Flash die. Address line A15 to
the Flash die is permanently grounded.
Seven of the pins and Micro
Cells on the PSD6XX die are reserved for generation of
Flash memory control signals. The address lines A14F, A16F, A17F, A18F, and the chip
select CSF are generated based on the FS0–7 inputs to the GPLD.
Refer to Appendix A for the operation and programming algorithm for the Flash memory.
SRAM
The SRAM has 4 Kbits of memory, organized as 512 x 8. The SRAM is enabled by the
chip select signal RS0 from the DPLD. The SRAM has a battery back-up (STBY) mode.
This back-up mode is automatically invoked when the V
CC
voltage drops under the
Vstdby voltage. The Vstdby voltage is connected only to the SRAM and cannot be lower
than 2.0 volts.
Memory Select Map
The Boot EPROM, Flash memory, and SRAM chip select equations are defined in the
ABEL file in terms of address and other DPLD inputs. The memory space for the Flash
chip select (FS0–7) should not be larger than the 16K Flash block it is selecting.
The Boot EPROM block should not be larger than 8 Kbytes.
The following rules govern how the PSD813F memory selects/space are defined:
J
The Flash blocks address space cannot overlap among blocks.
J
The Flash blocks address space cannot overlap the Boot EPROM, the SRAM and I/O
address space.
J
SRAM and internal I/O address space cannot overlap.
J
SRAM and internal I/O space can overlap Boot EPROM space, with priority given to
SRAM or I/O. The portion of Boot EPROM which is overlapped cannot be accessed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD82 | Three Phase Rectifier Bridges |
| PSD834F2V | Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM(2M位+256K位雙路閃速存儲(chǔ)器和64K位靜態(tài)RAM,閃速PSD,3.3V電源,用于8位MCU.) |
| PSD834F2 | Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的閃速ISP外圍) |
| PSD835G2 | Configurable Memory System on a Chip for 8-Bit Microcontrollers(8位微控制器片上存儲(chǔ)器可編程外設(shè)) |
| PSD835G2 | 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-254AA Tabless package; Similar to IRHMJ57160 with optional Total Dose Rating of 1000kRads |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD813FH-15J | 制造商:WSI 功能描述: |
| PSD813FH-90J | 制造商:WSI 功能描述: |
| PSD813FN-15J | 制造商:WSI 功能描述: |
| PSD833F2-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD833F2-90JI | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。