參數(shù)資料
型號： PSD813FH
英文描述： Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器)
中文描述： 場可編程微控制器外圍設備與快閃記憶體（帶閃存的現(xiàn)場可編程微控制器）
文件頁數(shù)： 5/83頁
文件大?。?/td> 369K
代理商： PSD813FH
Prelimnary
PSD813FN/FH
5
PSD813FN/FH
Architectural
Overview
(cont.)
Microcontroller Bus Interface
The PSD813FN/FH easily interfaces with most popular eight and sixteen-bit
microcontrollers with either multiplexed or non-multiplexed address/data busses. The
PSD813FH is for multiplexed applications and the PSD813FN is for non-multiplexed
applications. The PSD813FN/FH can operate with 16-bit MCUs if the MCU is configured for
8-bit external data path mode. The device is configured to respond to the microcontroller
control signals which are also used
as inputs to the PLDs.
Memory
The PSD813FN/FH contains a 1 Mbit Flash memory, a 256 Kbit Boot EPROM and a 4 Kbit
SRAM. The EPROM space and Flash memory space are divided into four and eight equally
sized blocks, respectively. Each block can be located in a different address space defined
by the user. The access time of either memory includes the address latching and DPLD
decoding. The Flash memory is implemented using a 4 Mbit (29040) device configured as a
1 Mbit memory. All the commands for the 29040 are applicable for operating as a 1 Mbit
Flash memory.
The 4 Kbit SRAM may be used as a scratch pad memory and an extension of the
microcontroller SRAM. The SRAM data is retained in the event of a system power down,
provided a backup battery is connected to the Vstby pin (PC2). Switching from the V
CC
supply to standby power occurs automatically when V
CC
drops below Vstby voltage.
Page Register
The four-bit Page Register expands the address range of the microcontroller by sixteen
times. The paged address can be used as part of the address space to access external
memory and peripherals or internal EPROM, SRAM and I/O.
Power Management Unit
The Power Management Unit (PMU) in the PSD813FN/FH enables the user to control the
power consumption on selected functional blocks based on system requirements. The PMU
includes an Automatic Power Down unit (APD) that will turn off device functions due to
microcontroller inactivity in one of two modes: the Power Down mode and Sleep mode.
Other power saving features, such as the CMiser in the PMU, allow the EPROM/SRAM to
operate at a slower rate to conserve power.
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相關代理商/技術參數(shù)
參數(shù)描述
PSD813FH-15J 制造商:WSI 功能描述:
PSD813FH-90J 制造商:WSI 功能描述:
PSD813FN-15J 制造商:WSI 功能描述:
PSD833F2-90J 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD833F2-90JI 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
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