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參數(shù)資料
| 型號： | PSD813FH |
| 英文描述： | Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器) |
| 中文描述： | 場可編程微控制器外圍設(shè)備與快閃記憶體（帶閃存的現(xiàn)場可編程微控制器） |
| 文件頁數(shù)： | 27/83頁 |
| 文件大小： | 369K |
| 代理商： | PSD813FH |
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Prelimnary
PSD813FN/FH
27
I/OPorts
There are four programmable I/O ports: Ports A, B are 8 bits, Port C is seven bits and
Port D is three bits. The ports can be configured to function in different modes of operation.
Each port pin is individually configurable allowing a single port to perform multiple functions.
The configuration is defined either using the PSDsoft tools or by the microcontroller writing
to on-chip registers.
General Port Architecture
The general architecture of the I/O Port is shown in Figure 12. Individual Port diagrams
are shown in Figures 14, 15 and 16, and will be discussed in the section below. If the
PSD813FN/FH is configured to a non-multiplexed bus mode, Port A and/or Port B are
connected to the MCU data bus and are not available as general purpose I/O ports.
As shown in Figure 12, the port pins contain an output multiplexer whose selects are driven
by the configuration defined in PSDabel and the Control Registers. Inputs to the multiplexer
include the following:
J
Output data from the Data Out Register in the MCU I/O output mode
J
Latched address outputs
J
GPLD Micro
Cell output or ECSPLD external chip select output
J
ECSPLD external chip select output
The above inputs are also connected to the Port Data Buffer (PDB) for feedback to the
Internal Data Bus that can be read by the microcontroller. The PDB is a three-state buffer
operating like a multiplexer that allows only one source to be read at a time. The PDB also
has inputs from the Direction Register, Control Register and direct port pin input (Data In ).
The Port pin’s tri-state output driver enable is controlled by a two input OR gate whose
inputs come from the GPLD AND array Enable product term (.oe) and the Direction
Register. If the enable product term of the array output is not defined, then the Direction
Register has sole control of the buffer. Refer to Tables 14 and 15 on how the direction of a
port pin is configured.
Drection Register Bit
0
1
Port Pin Mode
Input
Output
Table 14. Port Pin Drection Control,
Output Enable PT. Not Defined
Drection Register Bit
0
0
1
1
Output Enable PT.*
0
1
0
1
Port Pin Mode
Input
Output
Output
Output
Table 15. Port Pin Drection Control, Output Enable PT. Defined
*
Port D does not have an output enable P.T.
The register contents can be altered by the microcontroller. The PDB feedback path allows
the microcontroller to check the contents of the registers.
The A, B and C Ports have embedded Input Micro
Cells which can be configured as a
latch, a register or direct input to the GPLD. The latch and register are clocked by the
address strobe or a product term from the GPLD AND array. The output from the Input
Micro
Cell drives the PLD input bus and can be read by the microcontroller. Refer to the
Input Micro
Cell description in the PLD section.
Port A has additional logic (not shown in Figure 12) that enables it to operate in Peripheral
I/O mode when the PIO bit in the VM Register is set.
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