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參數(shù)資料
| 型號： | PSD813FH |
| 英文描述： | Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器) |
| 中文描述： | 場可編程微控制器外圍設(shè)備與快閃記憶體（帶閃存的現(xiàn)場可編程微控制器） |
| 文件頁數(shù)： | 7/83頁 |
| 文件大小： | 369K |
| 代理商： | PSD813FH |
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Prelimnary
PSD813FN/FH
7
The following table describes the pin names and pin functions of the PSD813FN/FH. Pins
that have multiple names and/or functions are defined by configuration.
Table 3.
PSD813FN/FH
Pin
Descriptions
Pin Name
Pin
Type
Function Description
ADIO0–7
30–37
I/O
Address/Data Port, interface to Microcontroller Bus
1. Input pins for multiplexed low order address/data byte.
ALE or AS latches address A0-7 for input to PLDs.
The PSD drives data out only if read is active and one of
the internal PSD functional blocks is selected.
A8–15
39–46
I/O
Address Port, interface to Microcontroller Bus
1. Address A8-15 inputs.
CNTL0
47
I
Write Input pin with multiple configurations. Depending on
the MCU interface selected, this pin can be:
1. WR – active low write input
2. R_W – read/write pin, low for write bus cycle
3. Control signal (CNTL0) input to PLD
(WR,
R_W)
CNTL1
50
I
Read or Data Strobe Input pin with multiple configurations.
Depending on the MCU interface selected, this pin can be:
1. RD – active low read input
2. E – E clock input.
During a write bus cycle, E is high and R/W is low
During a read bus cycle, E is high and R/W is high
3. DS – Data Strobe, active low
4. Control signal (CNTL1) input to PLD
(RD,
E, DS)
CNTL2
49
I
Read or other Control input pin with multiple configurations.
Depending on the MCU interface selected, this pin can be:
1. PSEN – Program Select enable, active low in code fetch
bus cycle
2. Control signal (CNTL2) input or general input to PLD
(PSEN)
Reset
48
I
Active low input. Resets I/O Ports, PLD Micro
Cells and
some of the Configuration Registers. Must be active at
power up.
PA0
PA1
PA2
PA3
29
28
27
25
I/O
Port A, PA0 – 3. This port is pin configurable and has
multiple functions:
1. MCU I/O – standard output or input port
2. External chip select (ECSPLD) output, or input to GPLD
3. Latched address outputs (see Table 4)
4. As Data Bus Port (D0–3) in non-multiplexed bus
configuration
5. Peripheral I/O mode
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD813FH-15J | 制造商:WSI 功能描述: |
| PSD813FH-90J | 制造商:WSI 功能描述: |
| PSD813FN-15J | 制造商:WSI 功能描述: |
| PSD833F2-90J | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD833F2-90JI | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
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