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參數(shù)資料
| 型號： | PSD813FH |
| 英文描述： | Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器) |
| 中文描述： | 場可編程微控制器外圍設(shè)備與快閃記憶體（帶閃存的現(xiàn)場可編程微控制器） |
| 文件頁數(shù)： | 81/83頁 |
| 文件大?。?/td> | 369K |
| 代理商： | PSD813FH |
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Prelimnary
PSD813FN/FH
81
Device Operation
(cont.)
Instructions and Commands
(cont.)
J
Error Bit D5
This bit is set to ‘1’ by the P/E.C. when there is a failure of byte programming, sector
erase, or bulk erase that results in invalid data being programmed in the memory sector.
In case of error in sector erase or byte program, the sector in which the error occurred
or to which the programmed byte belongs, must be discarded. Other sectors may still
be used. Error bit resets after Reset (RST) instruction. In case of success, the error
bit will set to ‘0’ during Program or Erase and to valid data after write operation is
completed.
J
Erase Time Bit D3
This bit is set to ‘0’ by the P/E.C. when the last sector Erase command has been
entered to the Command Interface and it is awaiting the Erase start. When the wait
period is finished, after 80 to 120 μs, D3 returns back to ‘1’.
J
Coded Cycles
The two coded cycles unlock the Command Interface. They are followed by a command
input or a command confirmation. The coded cycles consist of writing the data 0AAh at
address 5555h during the first cycle and data 55h at address 2AAAh during the second
cycle. Addresses are latched on the falling edge of WRF or CSF while data is latched
on the rising edge of WRF or CSF. The coded cycles happen on first and second cycles
of the command write or on the fourth and fifth cycles.
J
Reset (RST) Instruction
The Reset instruction consists of one write operation giving the command 0F0h. It can
be optionally preceded by the two coded cycles. After wait state of 5 μs, subsequent
read operations will read the memory array addressed and output the read byte.
J
Read Electronic Signature (RSIG) Instruction
This instruction uses the two coded cycles followed by one write cycle giving the
command 90h to address 5555h for command setup. A subsequent read will output the
manufacturer code or the device code depending on the levels of A0, A1, A6, A16, A17
and A18. The manufacturer code, 20h, is output when the addresses lines A0, A1 and
A6 are Low, the device code, 0E2h is output when A0 is High with A1 and A6 Low.
See Table 2.
J
Bulk Erase (BE) Instruction
This instruction uses six write cycles. The Erase Set-up command 80h is written to
address 5555h on third cycle after the two coded cycles. The Bulk Erase Confirm
command 10h is written at address 5555h on sixth cycle after another two coded cycles.
If the second command given is not an erase confirm or if the coded cycles are wrong,
the instruction aborts and the device is reset to Read Array. It is not necessary to
program the array with 00h first as the P/E.C. will automatically do this before erasing
to 0FFh. Read operations after the sixth rising edge of WRF or CSF output the status
register bits. During the execution of the erase by the P/E.C. the memory accepts
only the Reset (RST) command. Read of Data Polling bit D7 return ‘0’, then ‘1’ on
completion. The Toggle Bit D6 toggles during erase operation and stops when erase
is completed. After completion the Status Register bit D5 returns a ‘1’ if there has been
an Erase Failure because the erasure has not been verified even after the maximum
number of erase cycles have been executed.
Appendix A –
Flash Memory
(cont.)
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