參數(shù)資料
型號: PSD813FH
英文描述: Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器)
中文描述: 場可編程微控制器外圍設(shè)備與快閃記憶體(帶閃存的現(xiàn)場可編程微控制器)
文件頁數(shù): 33/83頁
文件大?。?/td> 369K
代理商: PSD813FH
Prelimnary
PSD813FN/FH
33
I/OPorts
(cont.)
Port Registers
(cont.)
Drive Register
The Drive Register configures the pin driver as Open Drain, or in the case of ECSPLD
outputs, sets the pin to operate in high slew rate. An external pull-up resistor is not required
when the pin is in the slew rate mode.
For Ports A and B the register sets different functions for the lower and higher nibbles. The
four upper bits set the corresponding bits the as CMOS (“0”) or Open Drain (“1”) driver. The
four lower bits are used for slew rate control. The slew rate is a measurement of the rise
and fall times of the output. A higher slew rate means a faster output response while a
lower slew rate is a slower, lower slope, response. The pin operates in high slew rate when
the corresponding bit in the Drive Register is set to “1”.
Table 20 shows the Drive Registers of Port A, B, C and D and which pin has the Open Drain
or Slew Rate configuration.
Drive
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port B
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port C
*
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
NA
Open
Drain
Open
Drain
Port D
NA
NA
NA
NA
NA
Slew
Rate
Slew
Rate
Slew
Rate
Table 20. Drive Register Pin Assignment
NOTE:
NA = Not Applicable, bit should set to “0”.
*
Port C pins are dedicated to Flash memory control in this multi-chip module product.
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