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參數(shù)資料
| 型號(hào)： | PSD813FH |
| 英文描述： | Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場(chǎng)可編程微控制器) |
| 中文描述： | 場(chǎng)可編程微控制器外圍設(shè)備與快閃記憶體（帶閃存的現(xiàn)場(chǎng)可編程微控制器） |
| 文件頁數(shù)： | 31/83頁 |
| 文件大?。?/td> | 369K |
| 代理商： | PSD813FH |
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Prelimnary
PSD813FN/FH
31
I/OPorts
(cont.)
Port Operating Modes
(cont.)
Address In Mode
For microcontrollers that have more than 16 address lines, the higher addresses can be
connected to Port A, B, or C. The address input can be latched in the Input Micro
Cell by
ALE. Any input that is included in the DPLD equations for the PSD Flash, OTP Boot, or
EPROM is considered as address input.
Data Port Mode
Port A can be used as a data bus port for a microcontroller with a non-multiplexed
address/data bus. The Data Port is connected to the data bus of the microcontroller. The
general I/O functions are disabled in Port A if the port is configured as Data Port. See
Figure 9.
Peripheral I/OMode
Only Port A supports the Peripheral I/O mode whereby all of Port A serves as a
tri-stateable bi-directional data buffer of the microcontroller’s data bus. Peripheral mode is
enabled by setting Bit 7 of the VM Register to a “1”. Figure 13 shows that when Peripheral
mode is enabled and either PSEL0 and PSEL1 from the DPLD is active, Port A acts as a
bi-directional buffer for the microcontroller D[7:0] data bus. The buffer is tri-stated when
PSEL 0 or 1 is not active. The Peripheral I/O mode can be used to interface with
external peripherals. Use PSDabel to write equations that contain the keyboards PSEL0
and PSEL1.
Open Drain/Slew Rate Mode
Ports A (pins PA7-4) and B (pins PB7-4) and C (except PC2) can be configured as open
drain instead of CMOS outputs. The Open Drain configuration is useful for sinking large
currents to operate LEDs, for example. The Open Drain mode is enabled by writing a “1” to
the corresponding bit in the Drive Register.
Port A (PA3–0), Port B (PB3–0) and Port D can be configured as ECSPLD outputs that
have a high slew rate. The high slew rate is enabled by writing a “1” to the corresponding
bit in the Drive Register.
RD
PSEL0
PSEL1
VM REGISTER BIT 7
WR
PA0-PA7
D0-D7
DATA BUS
Figure 13. Port A Peripheral Mode
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