參數(shù)資料
型號(hào): PSD813FH
英文描述: Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場(chǎng)可編程微控制器)
中文描述: 場(chǎng)可編程微控制器外圍設(shè)備與快閃記憶體(帶閃存的現(xiàn)場(chǎng)可編程微控制器)
文件頁(yè)數(shù): 8/83頁(yè)
文件大?。?/td> 369K
代理商: PSD813FH
PSD813FN/FH
Prelimnary
8
Pin Name
Pin Type
Function Description
PA4
PA5
PA6
PA7
24
23
22
21
I/O
Port A, PA4–7. This port is pin configurable and has
multiple functions:
1. MCU I/O – standard output or input port
2. GPLD Micro
Cell (McellAB) output or input
3. Latched address outputs (see Table 4)
4. As Data Bus Port (D4–7) in non-multiplexed bus
configuration
5. Peripheral I/O mode
CMOS
or
Open
Drain
PB0
PB1
PB2
PB3
7
6
5
4
I/O
Port B, PB0–3. This port is pin configurable and has
multiple functions:
1. MCU I/O – standard output or input port
2. External chip select (ECSPLD) output, or input to GPLD
3. Latched address outputs (see Table 4)
PB4
PB5
PB6
PB7
3
2
I/O
Port B, PB4–7. This port is pin configurable and has multiple
functions:
1. MCU I/O – standard output or input port
2. GPLD Micro
Cell (McellAB) output or input
3. Latched address outputs (see Table 4)
CMOS
or
Open
Drain
52
51
PC0 (WRF)
PC1 (RDF)
PC3 (A14F)
PC4 (A16F)
PC5 (A17F)
PC6 (A18F)
PC7 (CFS)
20
19
17
14
13
12
11
Flash Write
Flash Read
Flash Address A14
Flash Address A16
Flash Address A17
Flash Address A18
Flash Select
*
PC2
(Vstby)
18
I
Port C pin PC2.
Dedicated SRAM Standby Voltage Input. Pin should be
grounded if Vstby is not required.
PD0
(ALE)
10
I/O
Port D Pin PD0 can be configured as:
1. ALE input - latches addresses on ADIO0–15 pins
2. MCU I/O
3. GPLD input
4. ECSPLD output
PD1
(CLKIN)
9
I/O
Port D Pin PD1 can be configured as:
1. MCU I/O
2. GPLD input
3. External chip select (ECSPLD) output
4. CLKIN clock input – clock input to the GPLD Micro
Cells,
the APD power down counter and GPLD AND Array
Table 3.
PSD813FN/FH
Pin
Descriptions
(cont.)
*
These pins are reserved for internal Flash memory control and should not be used as outputs.
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