參數(shù)資料
型號(hào)： PSD813FH
英文描述： Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場(chǎng)可編程微控制器)
中文描述： 場(chǎng)可編程微控制器外圍設(shè)備與快閃記憶體（帶閃存的現(xiàn)場(chǎng)可編程微控制器）
文件頁(yè)數(shù)： 42/83頁(yè)
文件大?。?/td> 369K
代理商： PSD813FH
PSD813FN/FH
Prelimnary
42
VM Reg Bit 1
RD_EN
VM Reg Bit 0
PSEN_EN
Run-Time Mode
0
0
1
1
0
1
0
1
Separate Space Mode (default at reset)
Combined Program Space Mode
Combined Data Space Mode
Combined Space Mode
Table 25. VM Register
NOTE:
Bits 6-2 are not used. Use of bit 7 is described in the Peripheral I/O mode section.
Memory Select for 8031 Microcontrollers
The 8031 family of microcontrollers have a separate address space for program memory
(enabled by PSEN) and data memory (enabled by RD). Normally, the Boot EPROM would
lie in program address space and the SRAM would lie in data address space. The
PSD813FN/FH allows the Boot EPROM and SRAM address space to reside in program
space, data space or both. This flexibility enables several system designs. For example, if
the user desires to execute a program that resides in SRAM, the SRAM would have to
occupy program address space (enabled by PSEN). Likewise, the user may devote a block
of Boot EPROM to contain data lookup tables, requiring the Boot EPROM to occupy data
address space (enabled by RD).
The internal PSD Boot EPROM and SRAM each have their own output enable.
Combinations of PSEN and RD drive these output enables and are determined by bits set
at Run-Time by the MCU in the VM register (see Table 25). The schematic representation
can be seen in Figure 19 and the action of bit 0 and bit 1 of the VM register is shown.
There are four modes of operation that can be selected by the MCU at Run-Time as shown
in Table 25. All of these modes assume there are no overlapping address assignments for
blocks of Boot EPROM and SRAM. These blocks of memory may reside in the same 64K
program or data space, but not share any physical addresses within the 64K. Example 1:
Boot EPROM block 0 and SRAM cannot both start at address 0000. Example 2: Boot
EPROM block 2 in program space and Boot EPROM block 3 in data space cannot both
start at address 8000).
J
Separate Space Mode
Program memory space is separate from data memory space. This default state ties the
Boot EPROM output enable to PSEN only, and ties the SRAM output enable to RD only.
J
Combined ProgramSpace Mode
This mode allows the SRAM to reside in program space (to be enabled by PSEN
as well as RD).
J
Combined Data Space Mode
This mode allows the Boot EPROM to reside in data space (to be enabled by RD as
well as PSEN).
J
Combined Space Mode
This mode allows both the Boot EPROM and SRAM to reside in either program space
or data space (either memory may be accessed by PSEN or RD).
Memory Blocks
(cont.)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD813FH-15J 制造商:WSI 功能描述:
PSD813FH-90J 制造商:WSI 功能描述:
PSD813FN-15J 制造商:WSI 功能描述:
PSD833F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD833F2-90JI 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
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