參數(shù)資料
型號(hào)： W925E240
英文描述： Telephone Controller
中文描述： 電話控制器
文件頁數(shù)： 13/66頁
文件大小： 930K
代理商： W925E240
W925E/C240
8-bit CID Microcontroller
Revision : A6
-13-
Release Date : 2002/7/2
6.2
Special Function Registers
The W925E/C240 uses Special Function Registers (SFRs) to control and monitor peripherals and
their Modes.
The SFRs reside in the register locations 80-FFh and are accessed by direct addressing only.
Some of the SFRs are bit addressable. This is very useful in cases where one wishes to modify a
particular bit without changing the others. The SFRs that are bit addressable are those whose
addresses end in 0 or 8. The list of SFRs is as follows. The table is condensed with eight
locations per row. Empty locations indicate that there are no registers at these addresses. The
content of reserved bits or registers is not guaranteed.
Table 1 Special Function Register Location Table
F8
EIP
CIDGD
CIDGA
F0
B
E8
EIE
E0
ACC
D8
WDCON
D0
PSW
C8
DIVC
C0
SCON1
SBUF1
REGVC
B8
IP
DTMFG
COMPR
B0
P3
CIDR
CIDFG
CIDPCR
A8
IE
A0
P2
HB
P4H
98
P1EF
90
P1
EXIF
RPAGE
P1SR
88
TCON
TMOD
TL0
TL1
80
P0
SP
DPL
DPH
Note: The SFRs in the column with dark borders are bit-addressable.
A brief description of the SFRs now follows.
PMR
IRC1
FSKDR
P0IO
TH0
DPL1
STATUS
IRC2
DTMFDR DTMFPT
P1H
P1IO
TH1
DPH1
FSKTC
CASPT
FSKTB
CASAT
DTMFAT
P3H
P3IO
P4IO
P4
P2H
P2IO
CKCON1 CKCON2
DPS
PCON
PORT 0
(initial=FFh, input mode)
Bit:
7
6
5
4
3
2
1
0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Mnemonic: P0
Address: 80h
P0: P0 can be selected as input or output mode by the P0IO register. At initial reset, P0IO is
set to FFH, P0 is used as input mode. When P0IO is set to 0, the P0 is used as CMOS
open drain mode.
STACK POINTER
(initial=07H)
Bit:
7
6
5
4
3
2
1
0
SP.7
SP.6
SP.5
SP.4
SP.3
SP.2
SP.1
SP.0
Mnemonic: SP
Address: 81h
SP:
The Stack Pointer stores the scratchpad RAM address where the stack begins. In other
words, it always points to the top of the stack.
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