參數(shù)資料
型號： W925E240
英文描述： Telephone Controller
中文描述： 電話控制器
文件頁數(shù)： 2/66頁
文件大?。?/td> 930K
代理商： W925E240
W925E/C240
8-bit CID Microcontroller
Revision : A6
-2-
Release Date : 2002/7/2
F
IGURE
3-1 W925E/C240 P
IN
C
ONFIGURATION
..................................................................................................5
F
IGURE
6-1 P
ROGRAM
M
EMORY
M
AP
................................................................................................................10
F
IGURE
6-2
MEMORY MAP
....................................................................................................................................11
F
IGURE
6-3 S
CRATCHPAD
RAM/R
EGISTER
A
DDRESSING
..................................................................................12
F
IGURE
6-4 T
HE
S
TRUCTURE OF
CID F
LAGS
......................................................................................................36
F
IGURE
6-5 M
ODE
0 & M
ODE
1
OF
T
IMER
/C
OUNTER
0 & 1..............................................................................38
F
IGURE
6-6 M
ODE
2
OF
T
IMER
/C
OUNTER
0 & 1 ................................................................................................39
F
IGURE
6-7 W
ATCHDOG
T
IMER
...........................................................................................................................40
F
IGURE
6-8 T
IMING OF THE
S
ERIAL
P
ORT
1 I
NPUT
F
UNCTION
...........................................................................42
F
IGURE
6-9 T
IMING OF THE
S
ERIAL
P
ORT
1 O
UTPUT
F
UNCTION
.......................................................................42
F
IGURE
6-10 T
HE
C
ONFIGURATION OF
C
OMPARATOR
.......................................................................................43
F
IGURE
6-11 T
HE
R
ELATION
B
ETWEEN
DTMF
AND
K
EYPAD
...........................................................................43
F
IGURE
6-12 FSK M
ODULATOR
..........................................................................................................................44
F
IGURE
6-13 13/14-
BIT
D
IVIDER
.........................................................................................................................46
F
IGURE
6-14 T
HE
CID B
LOCK
D
IAGRAM
...........................................................................................................47
F
IGURE
6-15 A
PPLICATION
C
IRCUIT OF THE
R
ING
D
ETECTOR
...........................................................................48
F
IGURE
6-16 D
IFFERENTIAL
I
NPUT
G
AIN
C
ONTROL
C
IRCUIT
............................................................................49
F
IGURE
6-17 S
INGLE
-E
NDED
I
NPUT
G
AIN
C
ONTROL
C
IRCUIT
...........................................................................49
F
IGURE
6-18 G
UARD
T
IME
W
AVEFORM OF
A
LERT
T
ONE
S
IGNAL
D
ETECTION
................................................50
F
IGURE
6-19 T
HE
W
AVEFORM OF
DTMF D
ETECTION
.......................................................................................51
F
IGURE
6-20 FSK D
ETECTION
E
NABLE AND
FSK
C
ARRIER
P
RESENT AND
A
BSENT
T
IMING
..........................51
F
IGURE
6-21 S
ERIAL
D
ATA
I
NTERFACE
T
IMING OF
FSK D
EMODULATION
.......................................................52
F
IGURE
6-22 I
NTERNAL
CID G
AIN
C
ONTROL
R
EGISTER
S
ETTING
W
AVEFORM
...............................................53
F
IGURE
6-23 A
PPLICATION
C
IRCUIT OF
CID......................................................................................................54
F
IGURE
6-24 I
NPUT AND
O
UTPUT
T
IMING OF
B
ELLCORE
O
N
-
HOOK
D
ATA
T
RANSMISSION
.............................55
F
IGURE
6-25 I
NPUT AND
O
UTPUT
T
IMING OF
B
ELLCORE
O
FF
-
HOOK
D
ATA
T
RANSMISSION
............................56
F
IGURE
6-26 I
NPUT AND
O
UTPUT
T
IMING OF
BT I
DLE
S
TATE
(O
N
-
HOOK
) D
ATA
T
RANSMISSION
..................57
F
IGURE
6-27 I
NPUT AND
O
UTPUT
T
IMING OF
BT L
OOP
S
TATE
(O
FF
-
HOOK
) D
ATA
T
RANSMISSION
...............58
F
IGURE
6-28 I
NPUT AND
O
UTPUT
T
IMING OF
CCA C
ALLER
D
ISPLAY
S
ERVICE
D
ATA
T
RANSMISSION
..........59
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