參數(shù)資料
型號： W925E240
英文描述： Telephone Controller
中文描述： 電話控制器
文件頁數(shù)： 45/66頁
文件大?。?/td> 930K
代理商： W925E240
W925E/C240
8-bit CID Microcontroller
Revision : A6
-45-
Release Date : 2002/7/2
FTE:
FTM:
FDS:
LO0, LO1: FSK transmit level option
FSK transmit Enable. Enable=1, Disable=0
FSK signal Standard. Bellcore 202=1, V.23=0
FSK data sending status
FSK output level
150mV
120mV
95mV
75mV
LO1
0
0
1
1
LO0
0
1
0
1
FSK TRANSMIT DATA BUFFER
(initial=00H)
Bit:
7
6
5
4
3
2
1
0
FSKTB.7 FSKTB.6 FSKTB.5 FSKTB.4 FSKTB.3 FSKTB.2FSKTB.1 FSKTB.0
Mnemonic: FSKTB
Address: C7h
FSKTB.0:Only This bit will be latched and send out as FSK signal
When FTE enable will set the FDS to high to enable the internal latch clock in 1200Hz. When
FDS is in high state, FSKTB bit0 will be sent out by FSK modulator at the rising edge of latch
clock. FDS could be cleared by software to inform no more data will be sent out after the last bit is
sent completely. If the FDS is cleared then FTE will become low at next rising latch clock to
disable FSK modulator and clear FDS by hardware automatically.
When FTE is set, FSK modulation flag (FSF) will be set at every rising edge of latch clock to
produce an interrupt shared with CID interrupt routine. If a CID interrupt occurs, user can check
FSF to know if this interrupt is caused by FSK modulator. The only way to stop FSK signal
immediately is to disable FTE by software.
6.13
I/O Ports
There are five 8-bits ports named from P0 to P4 in W925E/C240. All ports can be configured as
input or output mode. Except P0, every port has pull high resistor enable/disable by PxH register.
After reset the initial state of each port is in input mode and the value of the registers from P0 to
P3 are FFh. The I/O port is described as below:
P0
: I/O mode is controlled by P0IO. Only
P0 output as open drain mode
and without pull high
resistor.
P1
: I/O mode is controlled by P1IO. Pull high is controlled by P1H.
P1.0~P1.3 work as INT2
,
P1.4~P1.7 work as INT3
.
Falling edge
on P1 pins to produce INT2 and INT3 flag. P1 is
configured as INT2/INT3 by P1EF register.
P2
: I/O mode is controlled by P2IO. Pull high is controlled by P2H.
P3
: I/O mode is controlled by P3IO. Pull high is controlled by P3H.
P3.5
T1
Timer/counter 1 external count input
P3.4
T0
Timer/counter 0 external count input
P3.3
INT1
External interrupt 1
P3.2
INT0
External interrupt 0
P4
: I/O mode is controlled by P4IO. Pull high is controlled by P4H.
Special function of P4 is described below.
P4.7-5
I/O
Normal I/O
P4.4
VPOS
Positive input of the comparator
P4.2
VNEG
Negative input of the comparator
P4.1
SDATA
Serial port output
P4.0
SCLK
Serial port input
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相關代理商/技術參數(shù)
參數(shù)描述
W925E240FG 功能描述:IC MCU 8-BIT W/CID 100-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:W925 標準包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI，I²C，UART/USART 外圍設備:POR，PWM，WDT 輸入/輸出數(shù):40 程序存儲器容量:- 程序存儲器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC（J 形引線） 包裝:帶卷 (TR)
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