參數(shù)資料
型號: W925E240
英文描述: Telephone Controller
中文描述: 電話控制器
文件頁數(shù): 17/66頁
文件大?。?/td> 930K
代理商: W925E240
W925E/C240
8-bit CID Microcontroller
Revision : A6
-17-
Release Date : 2002/7/2
CLOCK CONTROL1
(initial=00H)
Bit:
7
6
5
4
3
2
1
0
WD1
WD0
T1S1
T1S0
T0S1
T0S0
DIVS
M
/S
Mnemonic: CKCON1
Address: 8Eh
WD1-0: Watchdog timer mode select bits: These bits determine the time-out period for the
watchdog timer. In all four time-out options the reset time-out is 512 clocks more than the
interrupt time-out period.
WD1
WD0
Interrupt time-out
0
0
Fosc/2
12
0
1
Fosc/2
15
1
0
Fosc/2
18
1
1
Fosc/2
21
T0S0-1&T1S0-1: Timer0 & Timer1 clock source mode select bits. These bits determine the timer0
& timer1 clock source.
T0S1
(T1S1)
(T1S0)
source
0
0
Fosc/2
2
0
1
Fosc/2
6
1
0
Fosc/2
10
1
1
Fs
DIVS: Divider clock source control bit 1:
DIVS = 0 : Fs/2
DIVS= 1 : Fs/2
14
M/S:
System clock source control bit :
M
/S = 0 : Fosc = XIN1 ( F
M
)
M
/S = 1 : Fosc = XIN2 ( Fs)
Reset time-out
Fosc/2
12
+ 512
Fosc/2
15
+ 512
Fosc/2
18
+ 512
Fosc/2
21
+ 512
T0S0
Prescale clock
CLOCK CONTROL2
(initial=00H)
Bit:
7
6
5
4
3
-
2
-
1
-
0
-
ENBUZ BUZSL
KT1
KT0
Mnemonic: CKCON2
Address: 8Fh
ENBUZ: When ENBUZ=1 the BUZ pin works as buzzer output, otherwise BUZ pin is in floating
state.
BUZSL: Buzzer output selection. When BUZSL=0 BUZ is the output of octave tone. When
BUZZL=1, BUZ is the output of key tone.
KT1-0: Key tone frequency sources from divider. When divider is enable, KT1 and KT0
determines the key tone frequency.
key tone
frequency
0
0
Low
0
1
512Hz
1
0
1024Hz
1
1
2048Hz
KT1
KT0
PORT 1
(initial=FFh, input mode)
Bit:
7
6
5
4
3
2
1
0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
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