
W925E/C240
8-bit CID Microcontroller
Revision : A6
-15-
Release Date : 2002/7/2
POWER CONTROL
(initial=00H)
Bit:
7
-
6
5
4
3
2
1
PD
0
-
-
IDLT
GF1
GF0
IDL
Mnemonic: PCON
This bit controls the idle mode type. In idle mode when idle mode is released by any
interrupt, if IDLT=1 it will not jump to the corresponding interrupt; if IDLT=0 it will jump to
the corresponding interrupt.
GF1-0: These two bits are general purpose user flags.
PD:
Setting this bit causes the W925E/C240 to go into the POWER DOWN mode. In this
mode all the clocks are stopped and program execution is frozen. Power down mode
can be released by INT0~INT3 and ring detection of CID interrupt.
IDL:
Setting this bit causes the W925E/C240 to go into the IDLE mode. The type of idle
mode is selected by IDLT. In this mode the clocks to the CPU are stopped, so program
execution is frozen. But the clock path to the timers blocks and interrupt blocks is not
stopped, and these blocks continue operating.
Address: 87h
IDLT:
TIMER CONTROL
(initial=00H)
Bit:
7
6
5
4
3
2
IT1
1
0
TF1
TR1
TF0
TR0
IE1
IE0
IT0
Mnemonic: TCON
Address: 88h
TF1: Timer 1 overflow flag. This bit is set when Timer 1 overflows. It is cleared automatically
when the program does a timer 1 interrupt service routine. Software can also set or clear
this bit.
TR1: Timer 1 run control. This bit is set or cleared by software to turn timer on or off.
TF0: Timer 0 overflow flag. This bit is set when Timer 0 overflows. It is cleared automatically
when the program does a timer 0 interrupt service routine. Software can also set or clear
this bit.
TR0: Timer 0 run control. This bit is set or cleared by software to turn timer on or off.
IE1: Interrupt 1 edge detect: Set by hardware when an edge/level is detected on INT1. This bit
is cleared by hardware when the service routine is vectored to only if the interrupt was
edge triggered. Otherwise it follows the pin.
IT1: Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered
external inputs.
IE0: Interrupt 0 edge detect: Set by hardware when an edge/level is detected on INT0 . This bit
is cleared by hardware when the service routine is vectored to only if the interrupt was
edge triggered. Otherwise it follows the pin.
IT0: Interrupt 0 type control. Set/cleared by software to specify falling edge/ low level triggered
external inputs.
TIMER MODE CONTROL
(initial=00H)
Bit:
Mnemonic: TMOD
7
6
5
M1
4
M0
3
2
1
M1
0
M0
GATE
C/T
GATE
C/T
Address: 89h
Bit7~4 control timer 1, bit3~0 control timer0
GATE: Gating control. When this bit is set, Timer x is enabled only while
INTx
pin is high and
TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set.