參數(shù)資料
型號： W925E240
英文描述： Telephone Controller
中文描述： 電話控制器
文件頁數(shù)： 51/66頁
文件大?。?/td> 930K
代理商： W925E240
W925E/C240
8-bit CID Microcontroller
Revision : A6
-51-
Release Date : 2002/7/2
ESt
Vin (Tip/ring)
TONE #n
t
DP
t
GP
t
REC
t
DA
t
GA
t
ABS
DTMFD
*
1
2
3
3
DTMFDR
Tone #n-1
Tone #n
* ESt is an internal signal in the circuit.
+ Clear by software.
Figure 6-19 The Waveform of DTMF Detection
Tone Detector
In off-hook state, said type II system, detecting tone alert signal(CAS) is easily interfered by
human’s voice or other noise in voice band. Sometimes the interference makes falsely
recognizing a noise as a CAS(talk-off), or lost detecting a real CAS(talk-down). The DTMF can be
programmed as a tone detector by setting bit 4 of DTMFR2. The frequency band of the tone
detector is DTMF frequency from 697Hz to 1633Hz. Once the tone detector gets signals in the
band, the bit of DTMFH or DTMFL in register DTMFDR will become high immediately. User can
poll these 2 bits to check if the tone exists on the tip/ring. The input gain of tone detector is the
same as DTMF receiver.
FSK Decoder
The FSK carrier detector provides an indication of the present of a signal within the FSK
frequency band. If the output amplitude of the FSK band-pass filter is sufficient to be detected
continuously for 8 mS, the FSK carrier detected bit FCD will go high and it will be released if the
FSK band-pass filter output amplitude is not able to be detected for greater than 8 mS. The 8 mS
is the hysteresis of the FSK carrier detector. Figure 6-20 shows the timing of FSK carrier
detection.
1: Guard time timer is reset and starts to up count from 00H.
2: Guard time timer is reset and starts to up count from 00H.
3: The content of the up counting timer reaches the register DTMFPT/DTMFAT.
DTMFDF
+
Tip/Ring
FCD
Analog FSK Signal
t
CP
t
CA
FSKE
t
FSKE
Analog FSK Signal
t
CP
t
CA
Note
Figure 6-20 FSK Detection Enable and FSK Carrier Present and Absent Timing
The FSK demodulation function can demodulate Bell 202 and ITU-T V.23 Frequency Shift keying
(FSK) with 1200 baud rate. When the decoder receives the FSK serial data, the serial data will be
demodulated into bit FDATA with 1200 baud rate in the mean time the synchronous clock signal
is output to the bit FCLK. As the decoder receives one byte, the internal serial-to-parallel circuit
sets the bit FDR and converts the 8-bit serial data into the byte register FSKDR. The rising edge
of bit FDR will set the flag FDRF to produce CID interrupt but FDRF is cleared by software. User
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