參數(shù)資料
型號: W925E240
英文描述: Telephone Controller
中文描述: 電話控制器
文件頁數(shù): 34/66頁
文件大?。?/td> 930K
代理商: W925E240
W925E/C240
8-bit CID Microcontroller
Revision : A6
-34-
Release Date : 2002/7/2
6.5
Power Management
The W925E/C240 has 3 operation mode, normal mode, idle mode and power down mode to
manage the power consumption.
Normal Mode
Normal mode is used in the normal operation status. All functions can be worked in the normal
mode.
Idle Mode
The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that
sets the idle bit is the last instruction that will be executed before the device goes into Idle Mode.
In the Idle mode, the clock to the CPU is halted, but not to the Interrupt, Timer, Watchdog timer,
Divider, Comparator and CID blocks. This forces the CPU state to be frozen; the Program
counter, the Stack Pointer, the Program Status Word, the Accumulator and the other registers
hold their contents. The port pins hold the logical states they had at the time Idle was activated.
The Idle mode can be terminated in two ways. Since the interrupt controller is still active, the
activation of any enabled interrupt can wake up the processor. This will automatically terminate
the Idle mode and clear the Idle bit. And if bit IDLT(PCON.4) is cleared the Interrupt Service
Routine(ISR) will be executed, else the idle mode is released directly without any execution of
ISR. After the ISR, execution of the program will continue from the instruction, which put the
device into Idle mode.
The Idle mode can also be exited by activating the reset. The device can be put into reset either
by applying a low on the external RESET pin or a power on/fail reset condition or a Watchdog
timer reset. The external reset pin has to be held low for at least two machine cycles i.e. 8 clock
periods to be recognized as a valid reset. In the reset condition the program counter is reset to
0000h and all the SFRs are set to the reset condition. Since the clock is still running in the period
of external reset therefore the instruction is executed immediately. In the Idle mode, the
Watchdog timer continues to run, and if enabled, a time-out will cause a watchdog timer interrupt
which will wake up the device. The software must reset the Watchdog timer in order to preempt
the reset which will occur after 512 clock periods of the time-out.
Power Down Mode
The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that
does this will be the last instruction to be executed before the device goes into Power Down
mode. In the Power Down mode, all the clocks are stopped and the device comes to a halt. All
activity is completely stopped and the power consumption is reduced to the lowest possible value.
The port pins output the values held by their respective SFRs.
The W925E/C240 will exit the Power Down mode by reset or external interrupts or ring detected.
An external reset can be used to exit the Power down state. The low on RESET pin terminates
the Power Down mode, and restarts the clock. The on-chip hardware will now provide a delay of
65536 clock, which is used to provide time for the oscillator to restart and stabilize. Once this
delay is complete, an internal reset is activated and the program execution will restart from
0000h. In the Power down mode, the clock is stopped, so the Watchdog timer cannot be used to
provide the reset to exit Power down mode.
The W925E/C240 can be woken from the Power Down mode by forcing an external interrupt pin
activated and ring detected, provided the corresponding interrupt is enabled
,
while the global
enable(EA) bit is set. While the power down is released, the device will experience a warm-up
delay of 65536 clock cycles to ensure the stabilization of oscillation. Then device executes the
interrupt service routine for the corresponding external interrupt or CID interrupt. After the
interrupt service routine is completed, the program returns to the instruction after the one, which
put the device into Power Down mode and continues from there. When RGSL(PMR.5) bit is set to
1, the CPU will use the internal RC oscillator instead of crystal to exit Power Down mode. The
micro-controller will automatically switch from RC oscillator to crystal after a warm-up delay of
65536 crystal clocks. The RC oscillator runs at approximately 2
4 MHz. Using RC oscillator to
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