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參數(shù)資料
| 型號(hào)： | W925E240 |
| 英文描述： | Telephone Controller |
| 中文描述： | 電話控制器 |
| 文件頁數(shù)： | 36/66頁 |
| 文件大?。?/td> | 930K |
| 代理商： | W925E240 |
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W925E/C240
8-bit CID Microcontroller
Revision : A6
-36-
Release Date : 2002/7/2
The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the
time-out count is reached, the Watchdog timer interrupt flag WDIF (WDCON.3) is set. If the
enable bit EIE.5 enables the interrupt, then an interrupt will occur.
The Serial block can generate interrupts on reception or transmission. There are one interrupt
sources from the Serial block, which are obtained by SF1 in the SCON1. SF1 is cleared
automatically when the serial port interrupt is serviced.
The divider interrupt is generated by DIVF that is set when divider overflows. DIVF is set by
hardware and cleared when divider interrupt is serviced. The divider interrupt is enable/disable if
the bit EDIV is high/low.
The comparator interrupt is produced by COMPF, which is set when the RESC bit is changed
from low to high. RESC, which is the real-time result of comparator, is set when the voltage of
reference input is higher than the voltage of analog input.
The CID interrupt is generated by CIDF. The CIDF is a logic OR output of all CID flags which are
set by hardware and cleared by software. The structure of the CID flags is shown in Figure 6-4.
Each of the individual interrupts can be enabled or disabled by setting or clearing the
corresponding bits in the IE and EIE SFR. A bit EA, which is located in IE.7, is a global control bit
to enable/disable the all interrupt. When bit EA is zero all interrupts are disable and when bit EA
is high each interrupt is enable individually by the corresponding bit.
RNGF
FDRF
ALGOF
DTMFDF
FSF
CIDF
R
System clock
Clear by software
D
Figure 6-4 The Structure of CID Flags
Priority Level Structure
There are two priority levels for the interrupts, high and low. The interrupt sources can be
individually set to either high or low levels. Naturally, a higher priority interrupt cannot be
interrupted by a lower priority interrupt. However there exists a pre-defined hierarchy amongst the
interrupts themselves. This hierarchy comes into play when the interrupt controller has to resolve
simultaneous requests having the same priority level. This hierarchy is defined as shown below;
the interrupts are numbered starting from the highest priority to the lowest.
Table 4 Interrupt table.
Interrupt
Flag
Name
Location
External interrupt 0
IE0
TCON.1
EX0
Flag
EN Bit
EN Bit
Location
IE.0
Priority Flag Cleared
by
1
(higest)
software
2
hardware +
software
3
hardware +
software
4
hardware +
software
5
hardware +
software
6
hardware +
software
Interrupt
Vector
03h
hardware +
Timer0 overflow
TF0
TCON.5
ET0
IE.1
0Bh
External interrupt 1
IE1
TCON.3
EX1
IE.2
13h
Timer1 overflow
TF1
TCON.7
ET1
IE.3
1Bh
Serial port
SF1
SCON1.7
ES1
IE.6
3Bh
External interrupt 2
IE2
EXIF.0
EX2
EIE.0
43h
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| W925E240FG | 功能描述:IC MCU 8-BIT W/CID 100-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:W925 標(biāo)準(zhǔn)包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI，I²C，UART/USART 外圍設(shè)備:POR，PWM，WDT 輸入/輸出數(shù):40 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC（J 形引線） 包裝:帶卷 (TR) |
| W925E625 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8-bit CID MICROCONTROLLER |
| W925E625FG | 功能描述:IC MCU 8-BIT W/CID 160-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:W925 標(biāo)準(zhǔn)包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI，I²C，UART/USART 外圍設(shè)備:POR，PWM，WDT 輸入/輸出數(shù):40 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC（J 形引線） 包裝:帶卷 (TR) |
| W925EP01 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8-BIT CID MICROCONTROLLER |
| W925EP01FG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8-BIT CID MICROCONTROLLER |
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