參數(shù)資料
型號(hào)： W925E240
英文描述： Telephone Controller
中文描述： 電話控制器
文件頁數(shù)： 22/66頁
文件大?。?/td> 930K
代理商： W925E240
W925E/C240
8-bit CID Microcontroller
Revision : A6
-22-
Release Date : 2002/7/2
ALGO: Dual tone Alert signal Guard time detect signal. Set when a guard time qualified dual tone
alert signal has been detected. Cleared when the guard time qualified dual tone alert
signal is absent.
RNG: Ring detection bit. High to indicate the detection of line reversal and/or ringing.
CID FLAG GENERATOR
(initial=00H)
Bit:
Mnemonic: CIDFG
7
-
6
-
5
-
4
3
2
1
0
FSF
DTMFDF FDRF ALGOF RNGF
Address: B2h
FSF: Set when FSK Latch clock low to high. Cleared by software
DTMFDF: Set when DTMFD low to high. Cleared by software
FDRF: Set when FDR low to high. Cleared by software.
ALGOF: Set when ALGO low to high. Cleared by software.
RNGF: Set when RNG low to high. Cleared by software.
CID POWER CONTROL REGISTER
(initial=00H)
Bit:
Mnemonic: CIDPCR
7
-
6
-
5
-
4
3
-
2
1
0
CIDE
FSKE
Address: B3h
CASE DTMFE
CIDE: Global enable CID function. Low to disable all functions of CID parts.
FSKE: Enable FSK demodulation circuit.
CASE: Enable Dual Tone Alert Signal detection circuit.
DTMFE: Enable DTMF demodulation circuit.
FSK DATA REGISTER
(initial=XXH)
Bit:
Mnemonic: FSKDR
7
6
5
4
3
2
1
0
FD7
FD6
FD5
FD4
FD3
FD2
Address: B4h
FD1
FD0
FD7-0: 8 bits FSK demodulated data.
DTMF DATA REGISTER
(initial=XXH)
Bit:
Mnemonic: DTMFDR
7
6
5
4
3
2
1
0
CASH
CASL DTMFH DTMFL
DD3
DD2
Address: B5h
DD1
DD0
CASH: Set when Dual Tone Alert Signal high tone is detected.
CASL:
Set when Dual Tone Alert Signal low tone is detected.
DTMFH: Set when DTMF high tone is detected.
DTMFL: Set when DTMF low tone is detected.
DD3-0: 4 bits DTMF demodulated data.
DTMF PRESENT TIME REGISTER
(initial=19H)
Bit:
Mnemonic: DTMFPT
7
6
5
4
3
2
1
0
DPT7
DPT6
DPT5
DPT4
DPT3
DPT2
Address: B6h
DPT1
DPT0
The clock period of guard-time timer is 0.8582mS. The default DTMF present time is 21.45mS.
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