參數(shù)資料
型號(hào): W925E240
英文描述: Telephone Controller
中文描述: 電話控制器
文件頁(yè)數(shù): 42/66頁(yè)
文件大?。?/td> 930K
代理商: W925E240
W925E/C240
8-bit CID Microcontroller
Revision : A6
-42-
Release Date : 2002/7/2
received first. The I/O mode of serial clock pin is controlled by CLKIO. User has to take care the
initial state of the serial port pins.
C1
C2
C3
C4
SF1
REN1
Data Input
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SEDG=1, rising latch
SEDG=0, falling latch
NOTE: The serial clock frequency is fosc/2
Figure 6-8 Timing of the Serial Port 1 Input Function
C1
C2
C3
C4
Data output
SF1
Ins.
P4.1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SEDG=1, falling changed
NOTE: The serial clock frequency is fosc/2
Figure 6-9 Timing of the Serial Port 1 Output Function
Comparator
SEDG=0, rising changed
serial out
instruction
6.10
A built-in comparator to compare the analog signal. There is a analog input paths from pin VNEG.
Two reference inputs, one is from pin VPOS and other is from regulator output. When the voltage
of positive input is higher than the negative input, the comparator output will be high. The
RESEC(COMPR.3) is the result of the comparison. An internal rising signal on RESC produces
interrupt flag of COMPF (EXIF.4). The flag COMPF is cleared when comparator interrupt routine
is executed or cleared by software. Set COMPEN to enable the comparator function.
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