
W925E/C240
8-bit CID Microcontroller
EX3
EIE.1
Revision : A6
-37-
Release Date : 2002/7/2
External interrupt 3
IE3
EXIF.1
7
hardware +
software
software
hardware +
software
hardware +
software
software
4Bh
CID
CIDF
EXIF.2
ECID
EIE.2
8
53h
Divider overflow
DIVF
EXIF.3
EDIV
EIE.3
9
5Bh
Compare difference
COMPF
EXIF.4
ECOMP
EIE.4
10
63h
Watchdog timer
WDIF
WDCON.3
EWDI
EIE.5
11
(lowest)
6Bh
Ps: The flags marked as the italic font are not bit-addressable.
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled
interrupts are polled and their priority is resolved. If certain conditions are met then the hardware
will execute an internally generated LCALL instruction which will vector the process to the
appropriate interrupt vector address. The conditions for generating the LCALL are
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last machine cycle of the instruction currently being executed.
3. The current instruction does not involve a write to IP, IE, EIP or EIE registers and is not a RETI.
If any of these conditions is not met, then the LCALL will not be generated. The polling cycle is
repeated every machine cycle, with the interrupts being sampled in the same machine cycle. If an
interrupt flag is active in one cycle but not responded to, and is not active when the above
conditions are met, the denied interrupt will not be serviced. This means that active interrupts are
not remembered. Note that every polling cycle is new.
Execution continues from the vectored address until an RETI instruction is executed. On
execution of the RETI instruction, the processor pops out the top content of Stack to the PC. The
processor is not notified anything if the content of stack was changed. Note that a RET instruction
would perform exactly the same process as a RETI instruction, but it would not inform the
Interrupt Controller that the interrupt service routine is completed, and would leave the controller
still thinking that the service routine is underway.
6.8
Programmable Timers/Counters
The W925E/C240 has 2 16-bit timer/counters. There are two 8-bit registers to perform a 16-bit
counting register in every timer/counter. In timer/counter 0, TH0 is the upper 8 bits register and
TL0 is the lower 8 bits register. Similarly timer/counter 1 have two 8-bit registers, TH1 and TL1.
Each timer/counter has 4 kind of clock sources which are Fosc/4, Fosc/64, Fosc/1024 and Fs.
There are 3 operating modes in each timer/counter 0 and 1. The operating modes of timer/
counter0 is identical to timer/counter1. The overflow signal of each timer/counter is sampled at
phase 2 in every system machine cycle, therefore when the system clock and the timer/counter
clock both are from sub-oscillator, if the overflow frequency is higher than Fs/4 the overflow flag
can not be sampled correctly. Only one overflow flag can be sampled in a machine cycle others
will be missed.
MODE 0
In Mode 0, the timer/counters act as 13-bit timer/counters. The 13 bits consist of 8 bits of THx and
lower 5 bits of TLx. The upper 3 bits of TLx are ignored.
The negative edge of the clock causes the content of the TLx register to increase one. When the
fifth bit in TLx moves from 1 to 0, then the count in the THx register is incremented. When the
count in THx moves from FFh to 00h, then the overflow flag TFx is set. The counted input is
enabled only if TRx is set and either GATE=0 or
INTx
=1. When C/
T
is set to 0, then it will count
clock cycles, and if C/
T
is set to 1, then it will count 1 to 0 transitions on T0 (P3.4) for timer 0 and
T1 (P3.5) for timer 1. When the 13-bit count reaches 1FFFh, the next count will cause it to rollover