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參數(shù)資料
| 型號： | XPC750EC |
| 英文描述： | XPC750P/D XPC750P RISC Microprocessor Hardware Specifications |
| 中文描述： | XPC750P /數(shù)XPC750P RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 10/52頁 |
| 文件大?。?/td> | 1274K |
| 代理商： | XPC750EC |
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10
MPC755 RISC Microprocessor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Table 6 provides the DC electrical characteristics for the MPC755.
Table 7 provides the power consumption for the MPC755.
Table 6. DC Electrical Specifications
At recommended operating conditions (see Table 3)
Characteristic
Nominal
Bus
Voltage
1
Symbol
Min
Max
Unit
Notes
Input high voltage (all inputs except
SYSCLK)
2.5
V
IH
1.6
(L2)OV
DD
+ 0.3
V
2, 3
3.3
V
IH
2.0
(L2)OV
DD
+ 0.3
V
2, 3
Input low voltage (all inputs except
SYSCLK)
2.5
V
IL
–0.3
0.6
V
2
3.3
V
IL
–0.3
0.8
V
SYSCLK input high voltage
2.5
KV
IH
1.8
OV
DD
+ 0.3
V
3.3
KV
IH
2.4
OV
DD
+ 0.3
V
SYSCLK input low voltage
2.5
KV
IL
–0.3
0.4
V
3.3
KV
IL
–0.3
0.4
V
Input leakage current,
V
in
= L2OV
DD
/OV
DD
I
in
—
10
μA
2, 3
High-Z (off-state) leakage current,
V
in
= L2OV
DD
/OV
DD
I
TSI
—
10
μA
2, 3, 5
Output high voltage, I
OH
=
–6
mA
2.5
V
OH
1.7
—
V
3.3
V
OH
2.4
—
V
Output low voltage, I
OL
=
6
mA
2.5
V
OL
—
0.45
V
3.3
V
OL
—
0.4
V
Capacitance, V
in
= 0 V, f = 1 MHz
C
in
—
5.0
pF
3, 4
Notes:
1. Nominal voltages; see Table 3 for recommended operating conditions.
2. For processor bus signals, the reference is OV
DD
while L2OV
DD
is the reference for the L2 bus signals.
3. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG)
signals.
4. Capacitance is periodically sampled rather than 100% tested.
5. The leakage is measured for nominal OV
DD
and V
DD
, or both OV
DD
and V
DD
must vary in the same direction (for
example, both OV
DD
and V
DD
vary by either +5% or –5%).
Table 7. Power Consumption for MPC755
Processor (CPU) Frequency
350 MHz
Full-Power Mode
3.6
5.3
Doze Mode
2.0
Unit
Notes
300 MHz
400 MHz
450 MHz
Typical
Maximum
3.1
4.5
4.0
6.0
4.6
8.0
W
W
1, 3
1, 2
Maximum
1.8
2.3
2.8
W
1, 2
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