參數(shù)資料
型號(hào)： XPC750EC
英文描述： XPC750P/D XPC750P RISC Microprocessor Hardware Specifications
中文描述： XPC750P /數(shù)XPC750P RISC微處理器硬件規(guī)格
文件頁(yè)數(shù)： 37/52頁(yè)
文件大?。?/td> 1274K
代理商： XPC750EC
MOTOROLA
MPC755 RISC Microprocessor Hardware Specifications
37
System Design Information
Figure 23. Alternate Driver Impedance Measurement Circuit
Table 18 summarizes the signal impedance results. The driver impedance values were characterized at 0°,
65°, and 105°C. The impedance increases with junction temperature and is relatively unaffected by bus
voltage.
1.8.6
Pull-Up Resistor Requirements
The MPC755 requires pull-up resistors (1 k
5 k
) on several control pins of the bus interface to maintain
the control signals in the negated state after they have been actively negated and released by the MPC755
or other bus masters. These pins are TS, ABB, AACK, ARTRY, DBB, DBWO, TA, TEA, and DBDIS.
DRTRY should also be connected to a pull-up resistor (1 k
5 k
) if it will be used by the system;
otherwise, this signal should be connected to HRESET to select NO-DRTRY mode (see the
MPC750 RISC
Microprocessor Family User’s Manual
for more information on this mode).
Three test pins also require pull-up resistors (100
1 k
)
. These pins are L1_TSTCLK, L2_TSTCLK,
and LSSD_MODE. These signals are for factory use only and must be pulled up to OV
DD
for normal
machine operation.
In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor (1 k
5 k
) if it is
used by the system.
During inactive periods on the bus, the address and transfer attributes may not be driven by any master and
may, therefore, float in the high-impedance state for relatively long periods of time. Since the MPC755 must
continually monitor these signals for snooping, this float condition may cause additional power draw by the
input receivers on the MPC755 or by other receivers in the system. These signals can be pulled up through
weak (10 k
) pull-up resistors by the system or may be otherwise driven by the system during inactive
periods of the bus to avoid this additional power draw, but address bus pull-up resistors are not neccessary
Table 18. Impedance Characteristics
V
DD
= 2.0 V, OV
DD
= 3.3 V, T
j
= 0°
–
105°C
Impedance
Processor Bus
L2 Bus
Symbol
Unit
R
N
25–36
25–36
Z
0
R
P
26
–
39
26–39
Z
0
(L2)OV
DD
BGA
Pin
Data
V
force
OGND
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