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參數(shù)資料
| 型號： | XPC750EC |
| 英文描述： | XPC750P/D XPC750P RISC Microprocessor Hardware Specifications |
| 中文描述： | XPC750P /數(shù)XPC750P RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 12/52頁 |
| 文件大?。?/td> | 1274K |
| 代理商： | XPC750EC |
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12
MPC755 RISC Microprocessor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Figure 3 provides the SYSCLK input timing diagram.
Figure 3. SYSCLK Input Timing Diagram
1.4.2.2
Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC755 as defined in Figure 4 and
Figure 6. Timing specifications for the L2 bus are provided in Section 1.4.2.3, “L2 Clock AC
Specifications.”
SYSCLK jitter
—
±150
—
±150
—
±150
—
±150
ps
3, 4
Internal PLL relock
time
—
100
—
100
—
100
—
100
μ
s
3, 5
Notes:
1.
Caution:
The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK
(bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies. Refer to the PLL_CFG[0:3] signal description in Section 1.8.1, “PLL
Configuration
,”
for valid PLL_CFG[0:3] settings.
2. Rise and fall times measurements are now specified in terms of slew rates, rather than time to account for
selectable I/O bus interface levels. The minimum slew rate of 1 V/ns is equivalent to a 2 ns maximum rise/fall time
measured at 0.4 V and 2.4 V (OV
DD
= 3.3 V) or a rise/fall time of 1 ns measured at 0.4 V and 1.8 V (OV
DD
=
2.5 V).
3. Timing is guaranteed by design and characterization.
4.
This represents total input jitter—short term and long term combined—and is guaranteed by design.
5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time
required for PLL lock after a stable V
DD
and SYSCLK are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also
note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the
power-on reset sequence.
Table 8. Clock AC Timing Specifications (continued)
At recommended operating conditions (see Table 3)
Characteristic
Symbol
Maximum Processor Core Frequency
Unit
Notes
300 MHz
350 MHz
400 MHz
450 MHz
Min
Max
Min
Max
Min
Max
Min
Max
SYSCLK
VM
VM
VM
KV
IH
KV
IL
VM = Midpoint Voltage (OV
DD
/2)
t
SYSCLK
t
KR
t
KF
t
KHKL
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